32 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base)  in tmio_core_mmc_enable()  argument
35 	sd_config_write16(cnf, shift, CNF_CMD, SDCREN);  in tmio_core_mmc_enable()
36 	sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);  in tmio_core_mmc_enable()
39 	sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01);  in tmio_core_mmc_enable()
42 	sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f);  in tmio_core_mmc_enable()
45 	sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00);  in tmio_core_mmc_enable()
51 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base)  in tmio_core_mmc_resume()  argument
55 	sd_config_write16(cnf, shift, CNF_CMD, SDCREN);  in tmio_core_mmc_resume()
56 	sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);  in tmio_core_mmc_resume()
62 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state)  in tmio_core_mmc_pwr()  argument
64 	sd_config_write8(cnf, shift, CNF_PWR_CTL_2, state ? 0x02 : 0x00);  in tmio_core_mmc_pwr()
68 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state)  in tmio_core_mmc_clk_div()  argument
70 	sd_config_write8(cnf, shift, CNF_SD_CLK_MODE, state ? 1 : 0);  in tmio_core_mmc_clk_div()