97 				 unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_timing()  argument
102 	if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
103 	    shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&  in atmel_smc_cs_conf_set_timing()
104 	    shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
105 	    shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
106 	    shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)  in atmel_smc_cs_conf_set_timing()
116 	conf->timings &= ~GENMASK(shift + 3, shift);  in atmel_smc_cs_conf_set_timing()
117 	conf->timings |= val << shift;  in atmel_smc_cs_conf_set_timing()
139 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_setup()  argument
144 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&  in atmel_smc_cs_conf_set_setup()
145 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)  in atmel_smc_cs_conf_set_setup()
155 	conf->setup &= ~GENMASK(shift + 7, shift);  in atmel_smc_cs_conf_set_setup()
156 	conf->setup |= val << shift;  in atmel_smc_cs_conf_set_setup()
178 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_pulse()  argument
183 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&  in atmel_smc_cs_conf_set_pulse()
184 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)  in atmel_smc_cs_conf_set_pulse()
194 	conf->pulse &= ~GENMASK(shift + 7, shift);  in atmel_smc_cs_conf_set_pulse()
195 	conf->pulse |= val << shift;  in atmel_smc_cs_conf_set_pulse()
217 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_cycle()  argument
222 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)  in atmel_smc_cs_conf_set_cycle()
232 	conf->cycle &= ~GENMASK(shift + 15, shift);  in atmel_smc_cs_conf_set_cycle()
233 	conf->cycle |= val << shift;  in atmel_smc_cs_conf_set_cycle()