Lines Matching refs:str
57 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
60 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
63 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
66 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
69 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
72 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
75 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
78 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
81 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
84 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
87 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
90 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
93 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
96 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
103 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
106 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
109 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
112 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
115 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
118 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
126 str r1, [r4, r5]
149 str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
150 str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
153 str r1, [r0, #EMIF_SDRAM_TIMING_1]
154 str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
157 str r1, [r0, #EMIF_SDRAM_TIMING_2]
158 str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
161 str r1, [r0, #EMIF_SDRAM_TIMING_3]
162 str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
165 str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
166 str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
169 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
172 str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
175 str r1, [r0, #EMIF_COS_CONFIG]
178 str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
181 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
184 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
187 str r1, [r0, #EMIF_OCP_CONFIG]
194 str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
197 str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
200 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
203 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
206 str r1, [r0, #EMIF_DLL_CALIB_CTRL]
209 str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
212 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
223 str r1, [r4, r5]
236 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
264 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
292 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
294 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
320 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]