47 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3);  in s5p_cec_set_divider()
48 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2);  in s5p_cec_set_divider()
49 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1);  in s5p_cec_set_divider()
50 	writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0);  in s5p_cec_set_divider()
59 	writeb(reg, cec->reg + S5P_CEC_RX_CTRL);  in s5p_cec_enable_rx()
69 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);  in s5p_cec_mask_rx_interrupts()
79 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);  in s5p_cec_unmask_rx_interrupts()
89 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);  in s5p_cec_mask_tx_interrupts()
99 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);  in s5p_cec_unmask_tx_interrupts()
106 	writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);  in s5p_cec_reset()
107 	writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);  in s5p_cec_reset()
111 	writeb(reg, cec->reg + 0xc4);  in s5p_cec_reset()
116 	writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);  in s5p_cec_tx_reset()
123 	writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);  in s5p_cec_rx_reset()
127 	writeb(reg, cec->reg + 0xc4);  in s5p_cec_rx_reset()
132 	writeb(CEC_FILTER_THRESHOLD, cec->reg + S5P_CEC_RX_FILTER_TH);  in s5p_cec_threshold()
133 	writeb(0, cec->reg + S5P_CEC_RX_FILTER_CTRL);  in s5p_cec_threshold()
143 		writeb(data[i], cec->reg + (S5P_CEC_TX_BUFF0 + (i * 4)));  in s5p_cec_copy_packet()
147 	writeb(count, cec->reg + S5P_CEC_TX_BYTES);  in s5p_cec_copy_packet()
161 	writeb(reg, cec->reg + S5P_CEC_TX_CTRL);  in s5p_cec_copy_packet()
168 	writeb(addr & 0x0F, cec->reg + S5P_CEC_LOGIC_ADDR);  in s5p_cec_set_addr()
188 	writeb(S5P_CEC_IRQ_TX_DONE | S5P_CEC_IRQ_TX_ERROR,  in s5p_clr_pending_tx()
194 	writeb(S5P_CEC_IRQ_RX_DONE | S5P_CEC_IRQ_RX_ERROR,  in s5p_clr_pending_rx()