32 #define regr(reg)               readl((reg) + vpif_base)  macro
139 	regw((regr(reg)) | (0x01 << bit), reg);  in vpif_set_bit()
144 	regw(((regr(reg)) & ~(0x01 << bit)), reg);  in vpif_clr_bit()
221 #define channel0_intr_assert()	(regw((regr(VPIF_CH0_CTRL)|\
225 #define channel1_intr_assert()	(regw((regr(VPIF_CH1_CTRL)|\
229 #define channel2_intr_assert()	(regw((regr(VPIF_CH2_CTRL)|\
233 #define channel3_intr_assert()	(regw((regr(VPIF_CH3_CTRL)|\
274 		regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);  in enable_channel0()
276 		regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);  in enable_channel0()
283 		regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);  in enable_channel1()
285 		regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);  in enable_channel1()
296 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel0_intr_enable()
297 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel0_intr_enable()
299 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);  in channel0_intr_enable()
300 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),  in channel0_intr_enable()
303 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);  in channel0_intr_enable()
304 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),  in channel0_intr_enable()
318 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel1_intr_enable()
319 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel1_intr_enable()
321 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);  in channel1_intr_enable()
322 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),  in channel1_intr_enable()
325 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);  in channel1_intr_enable()
326 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),  in channel1_intr_enable()
429 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);  in enable_channel2()
430 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);  in enable_channel2()
432 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);  in enable_channel2()
433 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);  in enable_channel2()
441 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);  in enable_channel3()
442 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);  in enable_channel3()
444 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);  in enable_channel3()
445 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);  in enable_channel3()
457 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel2_intr_enable()
458 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel2_intr_enable()
459 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);  in channel2_intr_enable()
460 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),  in channel2_intr_enable()
463 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);  in channel2_intr_enable()
464 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),  in channel2_intr_enable()
478 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);  in channel3_intr_enable()
479 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);  in channel3_intr_enable()
481 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);  in channel3_intr_enable()
482 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),  in channel3_intr_enable()
485 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);  in channel3_intr_enable()
486 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),  in channel3_intr_enable()
611 	status = regr(VPIF_STATUS) & mask;  in vpif_intr_status()