95 	cx_write(MO_TS_LNGTH, dev->ts_packet_size);  in cx8802_start_dma()
108 		cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);  in cx8802_start_dma()
110 		cx_write(MO_PINMUX_IO, 0x00);  in cx8802_start_dma()
111 		cx_write(TS_HW_SOP_CNTRL, 0x47 << 16 | 188 << 4 | 0x01);  in cx8802_start_dma()
117 			cx_write(TS_SOP_STAT, 1 << 13);  in cx8802_start_dma()
120 			cx_write(TS_SOP_STAT, 0x00);  in cx8802_start_dma()
125 			cx_write(MO_PINMUX_IO, 0x88);  in cx8802_start_dma()
130 			cx_write(MO_PINMUX_IO, 0x88);  in cx8802_start_dma()
131 			cx_write(TS_SOP_STAT, 0);  in cx8802_start_dma()
132 			cx_write(TS_VALERR_CNTRL, 0);  in cx8802_start_dma()
136 			cx_write(MO_PINMUX_IO, 0x88);  in cx8802_start_dma()
137 			cx_write(TS_HW_SOP_CNTRL, (0x47 << 16) | (188 << 4));  in cx8802_start_dma()
139 			cx_write(TS_SOP_STAT, 0);  in cx8802_start_dma()
140 			cx_write(TS_VALERR_CNTRL, 0);  in cx8802_start_dma()
144 			cx_write(TS_SOP_STAT, 0x00);  in cx8802_start_dma()
147 		cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);  in cx8802_start_dma()
152 		cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */  in cx8802_start_dma()
155 		cx_write(TS_GEN_CNTRL, 0x46);  in cx8802_start_dma()
158 		cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */  in cx8802_start_dma()
159 		cx_write(TS_VALERR_CNTRL, 0x2000);  in cx8802_start_dma()
162 		cx_write(TS_GEN_CNTRL, 0x06);  in cx8802_start_dma()
171 	cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);  in cx8802_start_dma()
200 	cx_write(TS_GEN_CNTRL, 0xcd);  in cx8802_stop_dma()
321 	cx_write(MO_TS_INTSTAT, status);  in cx8802_mpeg_irq()
372 		cx_write(MO_PCI_INTSTAT, status);  in cx8802_irq()
382 		cx_write(MO_PCI_INTMSK, 0);  in cx8802_irq()