Lines Matching refs:NETUP_CI_FLG_RD
75 #define NETUP_CI_FLG_RD 1 macro
284 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_op_cam()
305 return altera_ci_op_cam(en50221, slot, 0, NETUP_CI_FLG_RD, addr, 0); in altera_ci_read_attribute_mem()
318 NETUP_CI_FLG_RD, addr, 0); in altera_ci_read_cam_ctl()
342 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_reset()
354 0, NETUP_CI_FLG_RD); in altera_ci_slot_reset()
389 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_ts_ctl()
409 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
410 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
540 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD); in altera_pid_control()
785 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_init()
789 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD); in altera_ci_init()
827 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_tuner_reset()