95 static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)  in ves1x93_writereg()  function
127 	ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);  in ves1x93_clr_bit()
128 	ves1x93_writereg (state, 0, state->init_1x93_tab[0]);  in ves1x93_clr_bit()
157 	return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);  in ves1x93_set_inversion()
163 		return ves1x93_writereg (state, 0x0d, 0x08);  in ves1x93_set_fec()
167 		return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);  in ves1x93_set_fec()
239 	ves1x93_writereg (state, 0x06, 0xff & BDR);  in ves1x93_set_symbolrate()
240 	ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));  in ves1x93_set_symbolrate()
241 	ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));  in ves1x93_set_symbolrate()
243 	ves1x93_writereg (state, 0x09, BDRI);  in ves1x93_set_symbolrate()
244 	ves1x93_writereg (state, 0x20, ADCONF);  in ves1x93_set_symbolrate()
245 	ves1x93_writereg (state, 0x21, FCONF);  in ves1x93_set_symbolrate()
256 	ves1x93_writereg (state, 0x05, AGCR);  in ves1x93_set_symbolrate()
278 			ves1x93_writereg (state, i, val);  in ves1x93_init()
292 		return ves1x93_writereg (state, 0x1f, 0x20);  in ves1x93_set_voltage()
294 		return ves1x93_writereg (state, 0x1f, 0x30);  in ves1x93_set_voltage()
296 		return ves1x93_writereg (state, 0x1f, 0x00);  in ves1x93_set_voltage()
385 	ves1x93_writereg (state, 0x18, 0x00);  /* reset the counter */  in ves1x93_read_ucblocks()
386 	ves1x93_writereg (state, 0x18, 0x80);  /* dto. */  in ves1x93_read_ucblocks()
437 	return ves1x93_writereg (state, 0x00, 0x08);  in ves1x93_sleep()
451 		return ves1x93_writereg(state, 0x00, 0x11);  in ves1x93_i2c_gate_ctrl()
453 		return ves1x93_writereg(state, 0x00, 0x01);  in ves1x93_i2c_gate_ctrl()