Lines Matching refs:write_reg
140 static int write_reg(struct stv *state, u16 reg, u8 val) in write_reg() function
192 status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); in write_shared_reg()
210 return write_reg(state, field >> 16, new); in write_field()
218 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
567 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
580 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
583 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
585 write_reg(state, RSTV0910_P2_ACLC2S28 + in tracking_optimization()
588 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
590 write_reg(state, RSTV0910_P2_ACLC2S216A + in tracking_optimization()
593 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
595 write_reg(state, RSTV0910_P2_ACLC2S232A + in tracking_optimization()
691 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + in get_bit_error_rate_s()
697 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + in get_bit_error_rate_s()
767 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
772 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
853 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); in set_mclock()
854 write_reg(state, RSTV0910_NCOARSE2, odf); in set_mclock()
855 write_reg(state, RSTV0910_NCOARSE1, ndiv); in set_mclock()
868 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
872 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
874 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
876 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
889 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
891 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
893 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
907 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
909 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
966 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
1009 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1032 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1058 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1060 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1063 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1067 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1074 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1075 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1080 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1081 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1082 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1083 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1084 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1085 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1087 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1088 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1089 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1090 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1096 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); in start()
1097 write_reg(state, RSTV0910_TSTRES0, 0); in start()
1101 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1103 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1111 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1113 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1116 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1118 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1121 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1122 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1124 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1126 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1140 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); in init_diseqc()
1141 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ in init_diseqc()
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ in init_diseqc()
1143 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq); in init_diseqc()
1161 write_reg(state, RSTV0910_P1_I2CRPT, 0x24); in probe()
1163 write_reg(state, RSTV0910_P2_I2CRPT, 0x24); in probe()
1165 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ in probe()
1167 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ in probe()
1168 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ in probe()
1169 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ in probe()
1170 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */ in probe()
1171 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ in probe()
1174 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */ in probe()
1176 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ in probe()
1178 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */ in probe()
1179 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */ in probe()
1181 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); in probe()
1182 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); in probe()
1183 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); in probe()
1184 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); in probe()
1186 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ in probe()
1187 write_reg(state, RSTV0910_TSTRES0, 0x00); in probe()
1189 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); in probe()
1190 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); in probe()
1192 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); in probe()
1193 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); in probe()
1198 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); in probe()
1200 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ in probe()
1201 write_reg(state, RSTV0910_P1_TSCFGL, 0x20); in probe()
1203 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed); in probe()
1205 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); in probe()
1207 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ in probe()
1208 write_reg(state, RSTV0910_P2_TSCFGL, 0x20); in probe()
1210 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed); in probe()
1213 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1214 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1215 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); in probe()
1216 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); in probe()
1218 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt); in probe()
1219 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt); in probe()
1221 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17); in probe()
1222 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff); in probe()
1224 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17); in probe()
1225 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff); in probe()
1253 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT : in gate_ctrl()
1422 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1425 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1427 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1464 write_reg(state, in read_status()
1472 write_reg(state, in read_status()
1477 write_reg(state, in read_status()
1485 write_reg(state, in read_status()
1493 write_reg(state, in read_status()
1498 write_reg(state, in read_status()
1504 write_reg(state, in read_status()
1652 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); in set_tone()
1654 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); in set_tone()