Lines Matching refs:regoff
93 u16 regoff; member
485 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
486 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
487 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
488 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
489 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
490 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
491 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); in get_cur_symbol_rate()
517 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_signal_parameters()
523 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_signal_parameters()
553 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); in tracking_optimization()
567 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
581 state->regoff, aclc); in tracking_optimization()
584 state->regoff, 0x2a); in tracking_optimization()
586 state->regoff, aclc); in tracking_optimization()
589 state->regoff, 0x2a); in tracking_optimization()
591 state->regoff, aclc); in tracking_optimization()
594 state->regoff, 0x2a); in tracking_optimization()
596 state->regoff, aclc); in tracking_optimization()
653 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, in get_signal_to_noise()
655 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, in get_signal_to_noise()
660 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, in get_signal_to_noise()
662 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, in get_signal_to_noise()
678 RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s()
692 state->regoff, in get_bit_error_rate_s()
698 state->regoff, 0x20 | in get_bit_error_rate_s()
752 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s2()
767 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
772 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
868 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
870 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); in stop()
872 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
874 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
876 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
889 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
891 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
893 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
907 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
909 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
966 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
999 RSTV0910_P2_NNOSDATAT1 + state->regoff, in set_vth()
1009 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1032 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1058 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1060 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1063 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1066 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); in start()
1067 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1074 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1075 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1080 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1081 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1082 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1083 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1084 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1085 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1087 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1088 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1089 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1090 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1101 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1103 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1111 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1113 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1116 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1118 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1121 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1122 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1124 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1126 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1305 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, in manage_matype_info()
1360 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); in read_signal_strength()
1365 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); in read_signal_strength()
1389 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); in read_status()
1392 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); in read_status()
1422 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1425 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1427 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1435 RSTV0910_P2_PDELSTATUS1 + state->regoff, in read_status()
1442 RSTV0910_P2_VSTATUSVIT + state->regoff, in read_status()
1465 RSTV0910_P2_DEMOD + state->regoff, in read_status()
1468 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1473 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1478 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1486 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1494 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1499 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1505 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1518 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, in read_status()
1578 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_frontend()
1584 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_frontend()
1792 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()