Lines Matching refs:ret
66 int ret; in mt312_read() local
79 ret = i2c_transfer(state->i2c, msg, 2); in mt312_read()
81 if (ret != 2) { in mt312_read()
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); in mt312_read()
100 int ret; in mt312_write() local
126 ret = i2c_transfer(state->i2c, &msg, 1); in mt312_write()
128 if (ret != 1) { in mt312_write()
129 dprintk("%s: ret == %d\n", __func__, ret); in mt312_write()
164 int ret; in mt312_get_inversion() local
167 ret = mt312_readreg(state, VIT_MODE, &vit_mode); in mt312_get_inversion()
168 if (ret < 0) in mt312_get_inversion()
169 return ret; in mt312_get_inversion()
179 int ret; in mt312_get_symbol_rate() local
186 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); in mt312_get_symbol_rate()
187 if (ret < 0) in mt312_get_symbol_rate()
188 return ret; in mt312_get_symbol_rate()
192 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
193 if (ret < 0) in mt312_get_symbol_rate()
194 return ret; in mt312_get_symbol_rate()
196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
197 if (ret < 0) in mt312_get_symbol_rate()
198 return ret; in mt312_get_symbol_rate()
205 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
206 if (ret < 0) in mt312_get_symbol_rate()
207 return ret; in mt312_get_symbol_rate()
209 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
210 if (ret < 0) in mt312_get_symbol_rate()
211 return ret; in mt312_get_symbol_rate()
215 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
216 if (ret < 0) in mt312_get_symbol_rate()
217 return ret; in mt312_get_symbol_rate()
237 int ret; in mt312_get_code_rate() local
240 ret = mt312_readreg(state, FEC_STATUS, &fec_status); in mt312_get_code_rate()
241 if (ret < 0) in mt312_get_code_rate()
242 return ret; in mt312_get_code_rate()
252 int ret; in mt312_initfe() local
256 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
258 if (ret < 0) in mt312_initfe()
259 return ret; in mt312_initfe()
265 ret = mt312_reset(state, 1); in mt312_initfe()
266 if (ret < 0) in mt312_initfe()
267 return ret; in mt312_initfe()
275 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); in mt312_initfe()
276 if (ret < 0) in mt312_initfe()
277 return ret; in mt312_initfe()
283 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
284 if (ret < 0) in mt312_initfe()
285 return ret; in mt312_initfe()
290 ret = mt312_write(state, HW_CTRL, buf, 2); in mt312_initfe()
291 if (ret < 0) in mt312_initfe()
292 return ret; in mt312_initfe()
295 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
296 if (ret < 0) in mt312_initfe()
297 return ret; in mt312_initfe()
299 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
300 if (ret < 0) in mt312_initfe()
301 return ret; in mt312_initfe()
312 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); in mt312_initfe()
313 if (ret < 0) in mt312_initfe()
314 return ret; in mt312_initfe()
316 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
317 if (ret < 0) in mt312_initfe()
318 return ret; in mt312_initfe()
330 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
331 if (ret < 0) in mt312_initfe()
332 return ret; in mt312_initfe()
338 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); in mt312_initfe()
339 if (ret < 0) in mt312_initfe()
340 return ret; in mt312_initfe()
342 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
343 if (ret < 0) in mt312_initfe()
344 return ret; in mt312_initfe()
353 int ret; in mt312_send_master_cmd() local
359 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_master_cmd()
360 if (ret < 0) in mt312_send_master_cmd()
361 return ret; in mt312_send_master_cmd()
363 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); in mt312_send_master_cmd()
364 if (ret < 0) in mt312_send_master_cmd()
365 return ret; in mt312_send_master_cmd()
367 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
370 if (ret < 0) in mt312_send_master_cmd()
371 return ret; in mt312_send_master_cmd()
378 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
379 if (ret < 0) in mt312_send_master_cmd()
380 return ret; in mt312_send_master_cmd()
392 int ret; in mt312_send_burst() local
398 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_burst()
399 if (ret < 0) in mt312_send_burst()
400 return ret; in mt312_send_burst()
402 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
404 if (ret < 0) in mt312_send_burst()
405 return ret; in mt312_send_burst()
416 int ret; in mt312_set_tone() local
422 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_set_tone()
423 if (ret < 0) in mt312_set_tone()
424 return ret; in mt312_set_tone()
426 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
428 if (ret < 0) in mt312_set_tone()
429 return ret; in mt312_set_tone()
454 int ret; in mt312_read_status() local
459 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); in mt312_read_status()
460 if (ret < 0) in mt312_read_status()
461 return ret; in mt312_read_status()
483 int ret; in mt312_read_ber() local
486 ret = mt312_read(state, RS_BERCNT_H, buf, 3); in mt312_read_ber()
487 if (ret < 0) in mt312_read_ber()
488 return ret; in mt312_read_ber()
499 int ret; in mt312_read_signal_strength() local
504 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); in mt312_read_signal_strength()
505 if (ret < 0) in mt312_read_signal_strength()
506 return ret; in mt312_read_signal_strength()
521 int ret; in mt312_read_snr() local
524 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); in mt312_read_snr()
525 if (ret < 0) in mt312_read_snr()
526 return ret; in mt312_read_snr()
536 int ret; in mt312_read_ucblocks() local
539 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); in mt312_read_ucblocks()
540 if (ret < 0) in mt312_read_ucblocks()
541 return ret; in mt312_read_ucblocks()
552 int ret; in mt312_set_frontend() local
588 ret = mt312_readreg(state, CONFIG, &config_val); in mt312_set_frontend()
589 if (ret < 0) in mt312_set_frontend()
590 return ret; in mt312_set_frontend()
596 ret = mt312_initfe(fe); in mt312_set_frontend()
597 if (ret < 0) in mt312_set_frontend()
598 return ret; in mt312_set_frontend()
604 ret = mt312_initfe(fe); in mt312_set_frontend()
605 if (ret < 0) in mt312_set_frontend()
606 return ret; in mt312_set_frontend()
644 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); in mt312_set_frontend()
645 if (ret < 0) in mt312_set_frontend()
646 return ret; in mt312_set_frontend()
657 int ret; in mt312_get_frontend() local
659 ret = mt312_get_inversion(state, &p->inversion); in mt312_get_frontend()
660 if (ret < 0) in mt312_get_frontend()
661 return ret; in mt312_get_frontend()
663 ret = mt312_get_symbol_rate(state, &p->symbol_rate); in mt312_get_frontend()
664 if (ret < 0) in mt312_get_frontend()
665 return ret; in mt312_get_frontend()
667 ret = mt312_get_code_rate(state, &p->fec_inner); in mt312_get_frontend()
668 if (ret < 0) in mt312_get_frontend()
669 return ret; in mt312_get_frontend()
679 int ret; in mt312_i2c_gate_ctrl() local
683 ret = mt312_readreg(state, GPP_CTRL, &val); in mt312_i2c_gate_ctrl()
684 if (ret < 0) in mt312_i2c_gate_ctrl()
697 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
700 return ret; in mt312_i2c_gate_ctrl()
706 int ret; in mt312_sleep() local
710 ret = mt312_reset(state, 1); in mt312_sleep()
711 if (ret < 0) in mt312_sleep()
712 return ret; in mt312_sleep()
716 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
717 if (ret < 0) in mt312_sleep()
718 return ret; in mt312_sleep()
721 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
722 if (ret < 0) in mt312_sleep()
723 return ret; in mt312_sleep()
726 ret = mt312_readreg(state, CONFIG, &config); in mt312_sleep()
727 if (ret < 0) in mt312_sleep()
728 return ret; in mt312_sleep()
731 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()
732 if (ret < 0) in mt312_sleep()
733 return ret; in mt312_sleep()