Lines Matching refs:mt312_writereg
142 static inline int mt312_writereg(struct mt312_state *state, in mt312_writereg() function
158 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); in mt312_reset()
192 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
205 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
256 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
283 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
295 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
299 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
316 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
330 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
342 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
367 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
378 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
402 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
426 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
448 return mt312_writereg(state, DISEQC_MODE, val); in mt312_set_voltage()
697 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
716 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
721 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
731 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()