Lines Matching refs:status
329 int status = 0; in WriteTable() local
334 while (!status) { in WriteTable()
347 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
350 return status; in WriteTable()
369 int status; in InitCE() local
373 status = WriteTable(state, state->m_InitCE); in InitCE()
374 if (status < 0) in InitCE()
382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
383 if (status < 0) in InitCE()
386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
387 if (status < 0) in InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
391 if (status < 0) in InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
395 if (status < 0) in InitCE()
400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
401 if (status < 0) in InitCE()
404 return status; in InitCE()
409 int status = 0; in StopOC() local
417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
418 if (status < 0) in StopOC()
425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
426 if (status < 0) in StopOC()
428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
429 if (status < 0) in StopOC()
431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
432 if (status < 0) in StopOC()
434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
435 if (status < 0) in StopOC()
439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
440 if (status < 0) in StopOC()
442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
443 if (status < 0) in StopOC()
448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
449 if (status < 0) in StopOC()
454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
455 if (status < 0) in StopOC()
460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
461 if (status < 0) in StopOC()
463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
464 if (status < 0) in StopOC()
466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
467 if (status < 0) in StopOC()
471 return status; in StopOC()
476 int status = 0; in StartOC() local
480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
481 if (status < 0) in StartOC()
485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
486 if (status < 0) in StartOC()
488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
489 if (status < 0) in StartOC()
493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
494 if (status < 0) in StartOC()
498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
499 if (status < 0) in StartOC()
502 return status; in StartOC()
537 int status; in DRX_GetLockStatus() local
541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
542 if (status < 0) { in DRX_GetLockStatus()
543 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); in DRX_GetLockStatus()
544 return status; in DRX_GetLockStatus()
567 int status; in SetCfgIfAgc() local
577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
578 if (status < 0) in SetCfgIfAgc()
582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
583 if (status < 0) in SetCfgIfAgc()
588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
589 if (status < 0) in SetCfgIfAgc()
606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
607 if (status < 0) in SetCfgIfAgc()
612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
613 if (status < 0) in SetCfgIfAgc()
620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
621 if (status < 0) in SetCfgIfAgc()
631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
632 if (status < 0) in SetCfgIfAgc()
634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
635 if (status < 0) in SetCfgIfAgc()
684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
685 if (status < 0) in SetCfgIfAgc()
687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
688 if (status < 0) in SetCfgIfAgc()
690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
691 if (status < 0) in SetCfgIfAgc()
693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
694 if (status < 0) in SetCfgIfAgc()
696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
697 if (status < 0) in SetCfgIfAgc()
707 return status; in SetCfgIfAgc()
712 int status = 0; in SetCfgRfAgc() local
725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
726 if (status < 0) in SetCfgRfAgc()
735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
736 if (status < 0) in SetCfgRfAgc()
739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
740 if (status < 0) in SetCfgRfAgc()
746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
747 if (status < 0) in SetCfgRfAgc()
753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
754 if (status < 0) in SetCfgRfAgc()
760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
761 if (status < 0) in SetCfgRfAgc()
777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
778 if (status < 0) in SetCfgRfAgc()
781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
782 if (status < 0) in SetCfgRfAgc()
788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
789 if (status < 0) in SetCfgRfAgc()
794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
795 if (status < 0) in SetCfgRfAgc()
805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
806 if (status < 0) in SetCfgRfAgc()
812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
813 if (status < 0) in SetCfgRfAgc()
828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
829 if (status < 0) in SetCfgRfAgc()
832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
833 if (status < 0) in SetCfgRfAgc()
839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
840 if (status < 0) in SetCfgRfAgc()
846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
847 if (status < 0) in SetCfgRfAgc()
853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
854 if (status < 0) in SetCfgRfAgc()
859 return status; in SetCfgRfAgc()
864 int status = 0; in ReadIFAgc() local
869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
871 if (status >= 0) { in ReadIFAgc()
899 return status; in ReadIFAgc()
930 int i, status = 0; in DownloadMicrocode() local
961 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
963 if (status < 0) in DownloadMicrocode()
969 return status; in DownloadMicrocode()
975 int status; in HI_Command() local
977 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
978 if (status < 0) in HI_Command()
979 return status; in HI_Command()
984 status = -1; in HI_Command()
987 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); in HI_Command()
988 } while (status != 0); in HI_Command()
990 if (status >= 0) in HI_Command()
991 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
992 return status; in HI_Command()
997 int status = 0; in HI_CfgCommand() local
1010 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1013 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
1015 return status; in HI_CfgCommand()
1028 int status; in HI_ResetCommand() local
1031 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1033 if (status == 0) in HI_ResetCommand()
1034 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1037 return status; in HI_ResetCommand()
1060 int status;
1072 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1073 if (status < 0)
1075 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1076 if (status < 0)
1078 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1079 if (status < 0)
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1082 if (status < 0)
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1085 if (status < 0)
1088 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1089 if (status < 0)
1094 if (status >= 0) {
1098 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1100 if (status < 0)
1107 return status;
1114 int status;
1118 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1122 return status;
1166 int status = 0; in ResetECOD() local
1169 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1171 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1173 if (!(status < 0)) in ResetECOD()
1174 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1175 if (!(status < 0)) in ResetECOD()
1176 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1177 return status; in ResetECOD()
1184 int status; in SetCfgPga() local
1191 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1192 if (status < 0) in SetCfgPga()
1196 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1197 if (status < 0) in SetCfgPga()
1201 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1202 if (status < 0) in SetCfgPga()
1206 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1207 if (status < 0) in SetCfgPga()
1212 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1213 if (status < 0) in SetCfgPga()
1219 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1220 if (status < 0) in SetCfgPga()
1224 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1225 if (status < 0) in SetCfgPga()
1229 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1230 if (status < 0) in SetCfgPga()
1234 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1235 if (status < 0) in SetCfgPga()
1240 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1241 if (status < 0) in SetCfgPga()
1245 return status; in SetCfgPga()
1250 int status; in InitFE() local
1253 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1254 if (status < 0) in InitFE()
1258 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1263 status = SetCfgPga(state, 0); in InitFE()
1265 status = in InitFE()
1271 if (status < 0) in InitFE()
1273 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1274 if (status < 0) in InitFE()
1276 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1277 if (status < 0) in InitFE()
1280 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1281 if (status < 0) in InitFE()
1286 return status; in InitFE()
1303 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); in SC_WaitForReady() local
1304 if (status == 0) in SC_WaitForReady()
1305 return status; in SC_WaitForReady()
1312 int status = 0, ret; in SC_SendCommand() local
1322 status = -1; in SC_SendCommand()
1325 return status; in SC_SendCommand()
1331 int ret, status = 0; in SC_ProcStartCommand() local
1338 status = -1; in SC_ProcStartCommand()
1349 return status; in SC_ProcStartCommand()
1355 int status; in SC_SetPrefParamCommand() local
1359 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1360 if (status < 0) in SC_SetPrefParamCommand()
1362 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1363 if (status < 0) in SC_SetPrefParamCommand()
1365 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1366 if (status < 0) in SC_SetPrefParamCommand()
1368 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1369 if (status < 0) in SC_SetPrefParamCommand()
1372 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1373 if (status < 0) in SC_SetPrefParamCommand()
1377 return status; in SC_SetPrefParamCommand()
1383 int status = 0;
1387 status = SC_WaitForReady(state);
1388 if (status < 0)
1390 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1391 if (status < 0)
1393 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1394 if (status < 0)
1398 return status;
1404 int status; in ConfigureMPEGOutput() local
1476 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1477 if (status < 0) in ConfigureMPEGOutput()
1479 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1480 if (status < 0) in ConfigureMPEGOutput()
1482 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1483 if (status < 0) in ConfigureMPEGOutput()
1485 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1486 if (status < 0) in ConfigureMPEGOutput()
1489 return status; in ConfigureMPEGOutput()
1494 int status = 0; in SetDeviceTypeId() local
1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1499 if (status < 0) in SetDeviceTypeId()
1502 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1503 if (status < 0) in SetDeviceTypeId()
1531 status = -1; in SetDeviceTypeId()
1537 if (status < 0) in SetDeviceTypeId()
1538 return status; in SetDeviceTypeId()
1583 return status; in SetDeviceTypeId()
1588 int status; in CorrectSysClockDeviation() local
1602 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1603 if (status < 0) in CorrectSysClockDeviation()
1605 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1606 if (status < 0) in CorrectSysClockDeviation()
1663 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1664 if (status < 0) in CorrectSysClockDeviation()
1668 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1669 if (status < 0) in CorrectSysClockDeviation()
1675 return status; in CorrectSysClockDeviation()
1680 int status; in DRX_Stop() local
1688 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1689 if (status < 0) in DRX_Stop()
1693 status = StopOC(state); in DRX_Stop()
1694 if (status < 0) in DRX_Stop()
1699 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1700 if (status < 0) in DRX_Stop()
1705 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1706 if (status < 0) in DRX_Stop()
1709 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1710 if (status < 0) in DRX_Stop()
1712 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1713 if (status < 0) in DRX_Stop()
1717 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1718 if (status < 0) in DRX_Stop()
1720 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1721 if (status < 0) in DRX_Stop()
1723 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1724 if (status < 0) in DRX_Stop()
1726 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1727 if (status < 0) in DRX_Stop()
1729 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1730 if (status < 0) in DRX_Stop()
1732 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1733 if (status < 0) in DRX_Stop()
1735 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1736 if (status < 0) in DRX_Stop()
1741 return status; in DRX_Stop()
1747 int status;
1751 status = -1;
1756 status = 0;
1761 status = -1;
1767 status = WriteTable(state, state->m_InitDiversityFront);
1770 status = WriteTable(state, state->m_InitDiversityEnd);
1776 status = WriteTable(state, state->m_DisableDiversity);
1781 if (!status)
1783 return status;
1789 int status = 0; in StartDiversity() local
1794 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1795 if (status < 0) in StartDiversity()
1798 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1799 if (status < 0) in StartDiversity()
1802 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1803 if (status < 0) in StartDiversity()
1806 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1807 if (status < 0) in StartDiversity()
1811 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1812 if (status < 0) in StartDiversity()
1820 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1821 if (status < 0) in StartDiversity()
1825 return status; in StartDiversity()
1870 int status = 0; in SetCfgNoiseCalibration() local
1873 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1874 if (status < 0) in SetCfgNoiseCalibration()
1880 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1881 if (status < 0) in SetCfgNoiseCalibration()
1884 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1885 if (status < 0) in SetCfgNoiseCalibration()
1889 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1890 if (status < 0) in SetCfgNoiseCalibration()
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1893 if (status < 0) in SetCfgNoiseCalibration()
1898 return status; in SetCfgNoiseCalibration()
1904 int status; in DRX_Start() local
1934 status = ResetECOD(state); in DRX_Start()
1935 if (status < 0) in DRX_Start()
1938 status = InitSC(state); in DRX_Start()
1939 if (status < 0) in DRX_Start()
1942 status = InitFT(state); in DRX_Start()
1943 if (status < 0) in DRX_Start()
1945 status = InitCP(state); in DRX_Start()
1946 if (status < 0) in DRX_Start()
1948 status = InitCE(state); in DRX_Start()
1949 if (status < 0) in DRX_Start()
1951 status = InitEQ(state); in DRX_Start()
1952 if (status < 0) in DRX_Start()
1954 status = InitSC(state); in DRX_Start()
1955 if (status < 0) in DRX_Start()
1961 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1962 if (status < 0) in DRX_Start()
1964 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1965 if (status < 0) in DRX_Start()
1977 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1978 if (status < 0) in DRX_Start()
1988 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
1989 if (status < 0) in DRX_Start()
2022 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2023 if (status < 0) in DRX_Start()
2025 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2026 if (status < 0) in DRX_Start()
2052 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2053 if (status < 0) in DRX_Start()
2055 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2056 if (status < 0) in DRX_Start()
2081 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2082 if (status < 0) in DRX_Start()
2084 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2085 if (status < 0) in DRX_Start()
2113 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2114 if (status < 0) in DRX_Start()
2116 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2117 if (status < 0) in DRX_Start()
2140 if (status < 0) in DRX_Start()
2150 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2151 if (status < 0) in DRX_Start()
2153 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2154 if (status < 0) in DRX_Start()
2156 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2157 if (status < 0) in DRX_Start()
2159 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2160 if (status < 0) in DRX_Start()
2162 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2163 if (status < 0) in DRX_Start()
2166 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2167 if (status < 0) in DRX_Start()
2169 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2170 if (status < 0) in DRX_Start()
2172 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2173 if (status < 0) in DRX_Start()
2175 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2176 if (status < 0) in DRX_Start()
2183 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2184 if (status < 0) in DRX_Start()
2186 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2187 if (status < 0) in DRX_Start()
2189 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2190 if (status < 0) in DRX_Start()
2192 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2193 if (status < 0) in DRX_Start()
2195 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2196 if (status < 0) in DRX_Start()
2199 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2200 if (status < 0) in DRX_Start()
2202 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2203 if (status < 0) in DRX_Start()
2205 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2206 if (status < 0) in DRX_Start()
2208 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2209 if (status < 0) in DRX_Start()
2217 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2218 if (status < 0) in DRX_Start()
2220 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2221 if (status < 0) in DRX_Start()
2223 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2224 if (status < 0) in DRX_Start()
2226 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2227 if (status < 0) in DRX_Start()
2229 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2230 if (status < 0) in DRX_Start()
2233 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2234 if (status < 0) in DRX_Start()
2236 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2237 if (status < 0) in DRX_Start()
2239 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2240 if (status < 0) in DRX_Start()
2242 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2243 if (status < 0) in DRX_Start()
2249 if (status < 0) in DRX_Start()
2257 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2258 if (status < 0) in DRX_Start()
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2264 if (status < 0) in DRX_Start()
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2275 if (status < 0) in DRX_Start()
2285 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2286 if (status < 0) in DRX_Start()
2293 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2294 if (status < 0) in DRX_Start()
2301 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2302 if (status < 0) in DRX_Start()
2309 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2310 if (status < 0) in DRX_Start()
2315 if (status < 0) in DRX_Start()
2334 status = Write16(state, in DRX_Start()
2341 status = Write16(state, in DRX_Start()
2348 status = Write16(state, in DRX_Start()
2352 status = -EINVAL; in DRX_Start()
2354 if (status < 0) in DRX_Start()
2357 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2358 if (status < 0) in DRX_Start()
2363 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2364 if (status < 0) in DRX_Start()
2377 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2378 if (status < 0) in DRX_Start()
2382 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2383 if (status < 0) in DRX_Start()
2388 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2389 if (status < 0) in DRX_Start()
2400 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2401 if (status < 0) in DRX_Start()
2403 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2404 if (status < 0) in DRX_Start()
2414 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2415 if (status < 0) in DRX_Start()
2417 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2418 if (status < 0) in DRX_Start()
2429 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2430 if (status < 0) in DRX_Start()
2434 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2435 if (status < 0) in DRX_Start()
2438 status = StartOC(state); in DRX_Start()
2439 if (status < 0) in DRX_Start()
2443 status = StartDiversity(state); in DRX_Start()
2444 if (status < 0) in DRX_Start()
2451 return status; in DRX_Start()
2609 int status = 0; in DRXD_init() local
2620 status = SetDeviceTypeId(state); in DRXD_init()
2621 if (status < 0) in DRXD_init()
2626 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2627 if (status < 0) in DRXD_init()
2634 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2635 if (status < 0) in DRXD_init()
2639 status = HI_ResetCommand(state); in DRXD_init()
2640 if (status < 0) in DRXD_init()
2643 status = StopAllProcessors(state); in DRXD_init()
2644 if (status < 0) in DRXD_init()
2646 status = InitCC(state); in DRXD_init()
2647 if (status < 0) in DRXD_init()
2676 status = InitHI(state); in DRXD_init()
2677 if (status < 0) in DRXD_init()
2679 status = InitAtomicRead(state); in DRXD_init()
2680 if (status < 0) in DRXD_init()
2683 status = EnableAndResetMB(state); in DRXD_init()
2684 if (status < 0) in DRXD_init()
2687 status = ResetCEFR(state); in DRXD_init()
2688 if (status < 0) in DRXD_init()
2692 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2693 if (status < 0) in DRXD_init()
2696 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2697 if (status < 0) in DRXD_init()
2710 status = InitFE(state); in DRXD_init()
2711 if (status < 0) in DRXD_init()
2713 status = InitFT(state); in DRXD_init()
2714 if (status < 0) in DRXD_init()
2716 status = InitCP(state); in DRXD_init()
2717 if (status < 0) in DRXD_init()
2719 status = InitCE(state); in DRXD_init()
2720 if (status < 0) in DRXD_init()
2722 status = InitEQ(state); in DRXD_init()
2723 if (status < 0) in DRXD_init()
2725 status = InitEC(state); in DRXD_init()
2726 if (status < 0) in DRXD_init()
2728 status = InitSC(state); in DRXD_init()
2729 if (status < 0) in DRXD_init()
2732 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2733 if (status < 0) in DRXD_init()
2735 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2736 if (status < 0) in DRXD_init()
2740 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2741 if (status < 0) in DRXD_init()
2743 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2744 if (status < 0) in DRXD_init()
2755 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2756 if (status < 0) in DRXD_init()
2759 status = StopOC(state); in DRXD_init()
2760 if (status < 0) in DRXD_init()
2765 status = 0; in DRXD_init()
2767 return status; in DRXD_init()
2802 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) in drxd_read_status() argument
2808 *status = 0; in drxd_read_status()
2812 *status |= FE_HAS_LOCK; in drxd_read_status()
2815 *status |= FE_HAS_LOCK; in drxd_read_status()
2818 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; in drxd_read_status()
2820 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; in drxd_read_status()