174 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)  in __dib8000_read_word()  argument
178 	state->i2c_write_buffer[0] = reg >> 8;  in __dib8000_read_word()
179 	state->i2c_write_buffer[1] = reg & 0xff;  in __dib8000_read_word()
181 	memset(state->msg, 0, 2 * sizeof(struct i2c_msg));  in __dib8000_read_word()
182 	state->msg[0].addr = state->i2c.addr >> 1;  in __dib8000_read_word()
183 	state->msg[0].flags = 0;  in __dib8000_read_word()
184 	state->msg[0].buf = state->i2c_write_buffer;  in __dib8000_read_word()
185 	state->msg[0].len = 2;  in __dib8000_read_word()
186 	state->msg[1].addr = state->i2c.addr >> 1;  in __dib8000_read_word()
187 	state->msg[1].flags = I2C_M_RD;  in __dib8000_read_word()
188 	state->msg[1].buf = state->i2c_read_buffer;  in __dib8000_read_word()
189 	state->msg[1].len = 2;  in __dib8000_read_word()
191 	if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)  in __dib8000_read_word()
194 	ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];  in __dib8000_read_word()
199 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)  in dib8000_read_word()  argument
203 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib8000_read_word()
208 	ret = __dib8000_read_word(state, reg);  in dib8000_read_word()
210 	mutex_unlock(&state->i2c_buffer_lock);  in dib8000_read_word()
215 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)  in dib8000_read32()  argument
219 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib8000_read32()
224 	rw[0] = __dib8000_read_word(state, reg + 0);  in dib8000_read32()
225 	rw[1] = __dib8000_read_word(state, reg + 1);  in dib8000_read32()
227 	mutex_unlock(&state->i2c_buffer_lock);  in dib8000_read32()
254 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)  in dib8000_write_word()  argument
258 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib8000_write_word()
263 	state->i2c_write_buffer[0] = (reg >> 8) & 0xff;  in dib8000_write_word()
264 	state->i2c_write_buffer[1] = reg & 0xff;  in dib8000_write_word()
265 	state->i2c_write_buffer[2] = (val >> 8) & 0xff;  in dib8000_write_word()
266 	state->i2c_write_buffer[3] = val & 0xff;  in dib8000_write_word()
268 	memset(&state->msg[0], 0, sizeof(struct i2c_msg));  in dib8000_write_word()
269 	state->msg[0].addr = state->i2c.addr >> 1;  in dib8000_write_word()
270 	state->msg[0].flags = 0;  in dib8000_write_word()
271 	state->msg[0].buf = state->i2c_write_buffer;  in dib8000_write_word()
272 	state->msg[0].len = 4;  in dib8000_write_word()
274 	ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?  in dib8000_write_word()
276 	mutex_unlock(&state->i2c_buffer_lock);  in dib8000_write_word()
382 static u16 fft_to_mode(struct dib8000_state *state)  in fft_to_mode()  argument
385 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {  in fft_to_mode()
401 static void dib8000_set_acquisition_mode(struct dib8000_state *state)  in dib8000_set_acquisition_mode()  argument
403 	u16 nud = dib8000_read_word(state, 298);  in dib8000_set_acquisition_mode()
406 	dib8000_write_word(state, 298, nud);  in dib8000_set_acquisition_mode()
410 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_output_mode()  local
413 	state->output_mode = mode;  in dib8000_set_output_mode()
416 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);  in dib8000_set_output_mode()
419 			&state->fe[0], mode);  in dib8000_set_output_mode()
432 		if (state->cfg.hostbus_diversity) {  in dib8000_set_output_mode()
449 		dib8000_set_acquisition_mode(state);  in dib8000_set_output_mode()
454 				&state->fe[0]);  in dib8000_set_output_mode()
458 	if (state->cfg.output_mpeg2_in_188_bytes)  in dib8000_set_output_mode()
461 	dib8000_write_word(state, 299, smo_mode);  in dib8000_set_output_mode()
462 	dib8000_write_word(state, 300, fifo_threshold);	/* synchronous fread */  in dib8000_set_output_mode()
463 	dib8000_write_word(state, 1286, outreg);  in dib8000_set_output_mode()
464 	dib8000_write_word(state, 1291, sram);  in dib8000_set_output_mode()
471 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_diversity_in()  local
472 	u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;  in dib8000_set_diversity_in()
475 	if (!state->differential_constellation) {  in dib8000_set_diversity_in()
476 		dib8000_write_word(state, 272, 1 << 9);	//dvsy_off_lmod4 = 1  in dib8000_set_diversity_in()
477 		dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2);	// sync_enable = 1; comb_mode = 2  in dib8000_set_diversity_in()
479 		dib8000_write_word(state, 272, 0);	//dvsy_off_lmod4 = 0  in dib8000_set_diversity_in()
480 		dib8000_write_word(state, 273, sync_wait);	// sync_enable = 0; comb_mode = 0  in dib8000_set_diversity_in()
482 	state->diversity_onoff = onoff;  in dib8000_set_diversity_in()
486 		dib8000_write_word(state, 270, 1);  in dib8000_set_diversity_in()
487 		dib8000_write_word(state, 271, 0);  in dib8000_set_diversity_in()
490 		dib8000_write_word(state, 270, 6);  in dib8000_set_diversity_in()
491 		dib8000_write_word(state, 271, 6);  in dib8000_set_diversity_in()
494 		dib8000_write_word(state, 270, 0);  in dib8000_set_diversity_in()
495 		dib8000_write_word(state, 271, 1);  in dib8000_set_diversity_in()
499 	if (state->revision == 0x8002) {  in dib8000_set_diversity_in()
500 		tmp = dib8000_read_word(state, 903);  in dib8000_set_diversity_in()
501 		dib8000_write_word(state, 903, tmp & ~(1 << 3));  in dib8000_set_diversity_in()
503 		dib8000_write_word(state, 903, tmp | (1 << 3));  in dib8000_set_diversity_in()
508 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)  in dib8000_set_power_mode()  argument
512 		reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,  in dib8000_set_power_mode()
515 	if (state->revision != 0x8090)  in dib8000_set_power_mode()
516 		reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;  in dib8000_set_power_mode()
518 		reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;  in dib8000_set_power_mode()
528 		if (state->revision != 0x8090)  in dib8000_set_power_mode()
534 		if (state->revision != 0x8090)  in dib8000_set_power_mode()
542 	dib8000_write_word(state, 774, reg_774);  in dib8000_set_power_mode()
543 	dib8000_write_word(state, 775, reg_775);  in dib8000_set_power_mode()
544 	dib8000_write_word(state, 776, reg_776);  in dib8000_set_power_mode()
545 	dib8000_write_word(state, 900, reg_900);  in dib8000_set_power_mode()
546 	dib8000_write_word(state, 1280, reg_1280);  in dib8000_set_power_mode()
549 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)  in dib8000_set_adc_state()  argument
552 	u16 reg, reg_907 = dib8000_read_word(state, 907);  in dib8000_set_adc_state()
553 	u16 reg_908 = dib8000_read_word(state, 908);  in dib8000_set_adc_state()
557 		if (state->revision != 0x8090) {  in dib8000_set_adc_state()
559 			ret |= dib8000_write_word(state, 908, reg_908);  in dib8000_set_adc_state()
562 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
564 			dib8000_write_word(state, 1925, reg |  in dib8000_set_adc_state()
568 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
571 			dib8000_write_word(state, 1925, reg & ~(1<<4));  in dib8000_set_adc_state()
573 			reg = dib8000_read_word(state, 921) & ~((0x3 << 14)  in dib8000_set_adc_state()
577 			dib8000_write_word(state, 921, reg | (1 << 14)  in dib8000_set_adc_state()
583 		if (state->revision == 0x8090) {  in dib8000_set_adc_state()
584 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
586 			dib8000_write_word(state, 1925,  in dib8000_set_adc_state()
614 	ret |= dib8000_write_word(state, 907, reg_907);  in dib8000_set_adc_state()
615 	ret |= dib8000_write_word(state, 908, reg_908);  in dib8000_set_adc_state()
622 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_bandwidth()  local
628 	if (state->timf == 0) {  in dib8000_set_bandwidth()
630 		timf = state->timf_default;  in dib8000_set_bandwidth()
633 		timf = state->timf;  in dib8000_set_bandwidth()
636 	dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));  in dib8000_set_bandwidth()
637 	dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));  in dib8000_set_bandwidth()
642 static int dib8000_sad_calib(struct dib8000_state *state)  in dib8000_sad_calib()  argument
646 	if (state->revision == 0x8090) {  in dib8000_sad_calib()
647 		dib8000_write_word(state, 922, (sad_sel << 2));  in dib8000_sad_calib()
648 		dib8000_write_word(state, 923, 2048);  in dib8000_sad_calib()
650 		dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);  in dib8000_sad_calib()
651 		dib8000_write_word(state, 922, (sad_sel << 2));  in dib8000_sad_calib()
654 		dib8000_write_word(state, 923, (0 << 1) | (0 << 0));  in dib8000_sad_calib()
655 		dib8000_write_word(state, 924, 776);  in dib8000_sad_calib()
658 		dib8000_write_word(state, 923, (1 << 0));  in dib8000_sad_calib()
659 		dib8000_write_word(state, 923, (0 << 0));  in dib8000_sad_calib()
668 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_wbd_ref()  local
671 	state->wbd_ref = value;  in dib8000_set_wbd_ref()
672 	return dib8000_write_word(state, 106, value);  in dib8000_set_wbd_ref()
675 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_co…  in dib8000_reset_pll_common()  argument
678 	if (state->revision != 0x8090) {  in dib8000_reset_pll_common()
679 		dib8000_write_word(state, 23,  in dib8000_reset_pll_common()
681 		dib8000_write_word(state, 24,  in dib8000_reset_pll_common()
684 		dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));  in dib8000_reset_pll_common()
685 		dib8000_write_word(state, 24,  in dib8000_reset_pll_common()
688 	dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));  in dib8000_reset_pll_common()
689 	dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));  in dib8000_reset_pll_common()
690 	dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));  in dib8000_reset_pll_common()
692 	if (state->revision != 0x8090)  in dib8000_reset_pll_common()
693 		dib8000_write_word(state, 922, bw->sad_cfg);  in dib8000_reset_pll_common()
696 static void dib8000_reset_pll(struct dib8000_state *state)  in dib8000_reset_pll()  argument
698 	const struct dibx000_bandwidth_config *pll = state->cfg.pll;  in dib8000_reset_pll()
701 	if (state->revision != 0x8090) {  in dib8000_reset_pll()
702 		dib8000_write_word(state, 901,  in dib8000_reset_pll()
710 		dib8000_write_word(state, 902, clk_cfg1);  in dib8000_reset_pll()
712 		dib8000_write_word(state, 902, clk_cfg1);  in dib8000_reset_pll()
717 		if (state->cfg.pll->ADClkSrc == 0)  in dib8000_reset_pll()
718 			dib8000_write_word(state, 904,  in dib8000_reset_pll()
722 		else if (state->cfg.refclksel != 0)  in dib8000_reset_pll()
723 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |  in dib8000_reset_pll()
724 					((state->cfg.refclksel & 0x3) << 10) |  in dib8000_reset_pll()
728 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |  in dib8000_reset_pll()
732 		dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |  in dib8000_reset_pll()
736 		reg = dib8000_read_word(state, 1857);  in dib8000_reset_pll()
737 		dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));  in dib8000_reset_pll()
739 		reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */  in dib8000_reset_pll()
740 		dib8000_write_word(state, 1858, reg | 1);  in dib8000_reset_pll()
742 		dib8000_write_word(state, 904, (pll->modulo << 8));  in dib8000_reset_pll()
745 	dib8000_reset_pll_common(state, pll);  in dib8000_reset_pll()
751 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_update_pll()  local
752 	u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);  in dib8000_update_pll()
753 	u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;  in dib8000_update_pll()
765 	if (state->revision == 0x8090) {  in dib8000_update_pll()
767 		reg_1857 = dib8000_read_word(state, 1857);  in dib8000_update_pll()
769 		dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));  in dib8000_update_pll()
771 		dib8000_write_word(state, 1856, reg_1856 |  in dib8000_update_pll()
776 		internal = dib8000_read32(state, 23) / 1000;  in dib8000_update_pll()
783 		dib8000_write_word(state, 23,  in dib8000_update_pll()
785 		dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));  in dib8000_update_pll()
787 		dib8000_write_word(state, 1857, reg_1857 | (1 << 15));  in dib8000_update_pll()
789 		while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)  in dib8000_update_pll()
793 		reg_1856 = dib8000_read_word(state, 1856);  in dib8000_update_pll()
797 		if (bw != state->current_demod_bw) {  in dib8000_update_pll()
799 …h Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldpredi…  in dib8000_update_pll()
801 			if (state->cfg.pll->pll_prediv != oldprediv) {  in dib8000_update_pll()
805 …g for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg…  in dib8000_update_pll()
806 				dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */  in dib8000_update_pll()
807 				dib8000_reset_pll(state);  in dib8000_update_pll()
808 				dib8000_write_word(state, 898, 0x0004); /* sad */  in dib8000_update_pll()
810 				ratio = state->cfg.pll->pll_ratio;  in dib8000_update_pll()
812 			state->current_demod_bw = bw;  in dib8000_update_pll()
817 			dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio);  in dib8000_update_pll()
818 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL …  in dib8000_update_pll()
858 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_gpio()  local
859 	return dib8000_cfg_gpio(state, num, dir, val);  in dib8000_set_gpio()
1000 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_reset_stats()  local
1001 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_reset_stats()
1028 	state->init_ucb = -ucb;  in dib8000_reset_stats()
1029 	state->ber_jiffies_stats = 0;  in dib8000_reset_stats()
1030 	state->per_jiffies_stats = 0;  in dib8000_reset_stats()
1031 	memset(&state->ber_jiffies_stats_layer, 0,  in dib8000_reset_stats()
1032 	       sizeof(state->ber_jiffies_stats_layer));  in dib8000_reset_stats()
1037 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_reset()  local
1039 	if ((state->revision = dib8000_identify(&state->i2c)) == 0)  in dib8000_reset()
1043 	if (state->revision != 0x8090)  in dib8000_reset()
1044 		dib8000_write_word(state, 1287, 0x0003);  in dib8000_reset()
1046 	if (state->revision == 0x8000)  in dib8000_reset()
1049 	dibx000_reset_i2c_master(&state->i2c_master);  in dib8000_reset()
1051 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_reset()
1054 	dib8000_set_adc_state(state, DIBX000_ADC_OFF);  in dib8000_reset()
1057 	dib8000_write_word(state, 770, 0xffff);  in dib8000_reset()
1058 	dib8000_write_word(state, 771, 0xffff);  in dib8000_reset()
1059 	dib8000_write_word(state, 772, 0xfffc);  in dib8000_reset()
1060 	dib8000_write_word(state, 898, 0x000c);	/* restart sad */  in dib8000_reset()
1061 	if (state->revision == 0x8090)  in dib8000_reset()
1062 		dib8000_write_word(state, 1280, 0x0045);  in dib8000_reset()
1064 		dib8000_write_word(state, 1280, 0x004d);  in dib8000_reset()
1065 	dib8000_write_word(state, 1281, 0x000c);  in dib8000_reset()
1067 	dib8000_write_word(state, 770, 0x0000);  in dib8000_reset()
1068 	dib8000_write_word(state, 771, 0x0000);  in dib8000_reset()
1069 	dib8000_write_word(state, 772, 0x0000);  in dib8000_reset()
1070 	dib8000_write_word(state, 898, 0x0004);	// sad  in dib8000_reset()
1071 	dib8000_write_word(state, 1280, 0x0000);  in dib8000_reset()
1072 	dib8000_write_word(state, 1281, 0x0000);  in dib8000_reset()
1075 	if (state->revision != 0x8090) {  in dib8000_reset()
1076 		if (state->cfg.drives)  in dib8000_reset()
1077 			dib8000_write_word(state, 906, state->cfg.drives);  in dib8000_reset()
1081 			dib8000_write_word(state, 906, 0x2d98);  in dib8000_reset()
1085 	dib8000_reset_pll(state);  in dib8000_reset()
1086 	if (state->revision != 0x8090)  in dib8000_reset()
1087 		dib8000_write_word(state, 898, 0x0004);  in dib8000_reset()
1089 	if (dib8000_reset_gpio(state) != 0)  in dib8000_reset()
1092 	if ((state->revision != 0x8090) &&  in dib8000_reset()
1096 	state->current_agc = NULL;  in dib8000_reset()
1100 	if (state->cfg.pll->ifreq == 0)  in dib8000_reset()
1101 		dib8000_write_word(state, 40, 0x0755);	/* P_iqc_corr_inh = 0 enable IQcorr block */  in dib8000_reset()
1103 		dib8000_write_word(state, 40, 0x1f55);	/* P_iqc_corr_inh = 1 disable IQcorr block */  in dib8000_reset()
1113 				dib8000_write_word(state, r, *n++);  in dib8000_reset()
1120 	state->isdbt_cfg_loaded = 0;  in dib8000_reset()
1123 	if ((state->revision != 8090) && (state->cfg.div_cfg != 0))  in dib8000_reset()
1124 		dib8000_write_word(state, 903, state->cfg.div_cfg);  in dib8000_reset()
1127 	dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));  in dib8000_reset()
1131 	dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);  in dib8000_reset()
1132 	dib8000_sad_calib(state);  in dib8000_reset()
1133 	if (state->revision != 0x8090)  in dib8000_reset()
1134 		dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);  in dib8000_reset()
1137 	dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));  in dib8000_reset()
1139 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);  in dib8000_reset()
1146 static void dib8000_restart_agc(struct dib8000_state *state)  in dib8000_restart_agc()  argument
1149 	dib8000_write_word(state, 770, 0x0a00);  in dib8000_restart_agc()
1150 	dib8000_write_word(state, 770, 0x0000);  in dib8000_restart_agc()
1153 static int dib8000_update_lna(struct dib8000_state *state)  in dib8000_update_lna()  argument
1157 	if (state->cfg.update_lna) {  in dib8000_update_lna()
1159 		dyn_gain = dib8000_read_word(state, 390);  in dib8000_update_lna()
1161 		if (state->cfg.update_lna(state->fe[0], dyn_gain)) {  in dib8000_update_lna()
1162 			dib8000_restart_agc(state);  in dib8000_update_lna()
1169 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)  in dib8000_set_agc_config()  argument
1175 	if (state->current_band == band && state->current_agc != NULL)  in dib8000_set_agc_config()
1177 	state->current_band = band;  in dib8000_set_agc_config()
1179 	for (i = 0; i < state->cfg.agc_config_count; i++)  in dib8000_set_agc_config()
1180 		if (state->cfg.agc[i].band_caps & band) {  in dib8000_set_agc_config()
1181 			agc = &state->cfg.agc[i];  in dib8000_set_agc_config()
1190 	state->current_agc = agc;  in dib8000_set_agc_config()
1193 	dib8000_write_word(state, 76, agc->setup);  in dib8000_set_agc_config()
1194 	dib8000_write_word(state, 77, agc->inv_gain);  in dib8000_set_agc_config()
1195 	dib8000_write_word(state, 78, agc->time_stabiliz);  in dib8000_set_agc_config()
1196 	dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);  in dib8000_set_agc_config()
1199 	dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);  in dib8000_set_agc_config()
1200 	dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);  in dib8000_set_agc_config()
1203 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag…  in dib8000_set_agc_config()
1206 	if (state->wbd_ref != 0)  in dib8000_set_agc_config()
1207 		dib8000_write_word(state, 106, state->wbd_ref);  in dib8000_set_agc_config()
1209 		dib8000_write_word(state, 106, agc->wbd_ref);  in dib8000_set_agc_config()
1211 	if (state->revision == 0x8090) {  in dib8000_set_agc_config()
1212 		reg = dib8000_read_word(state, 922) & (0x3 << 2);  in dib8000_set_agc_config()
1213 		dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));  in dib8000_set_agc_config()
1216 	dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));  in dib8000_set_agc_config()
1217 	dib8000_write_word(state, 108, agc->agc1_max);  in dib8000_set_agc_config()
1218 	dib8000_write_word(state, 109, agc->agc1_min);  in dib8000_set_agc_config()
1219 	dib8000_write_word(state, 110, agc->agc2_max);  in dib8000_set_agc_config()
1220 	dib8000_write_word(state, 111, agc->agc2_min);  in dib8000_set_agc_config()
1221 	dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);  in dib8000_set_agc_config()
1222 	dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);  in dib8000_set_agc_config()
1223 	dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);  in dib8000_set_agc_config()
1224 	dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);  in dib8000_set_agc_config()
1226 	dib8000_write_word(state, 75, agc->agc1_pt3);  in dib8000_set_agc_config()
1227 	if (state->revision != 0x8090)  in dib8000_set_agc_config()
1228 		dib8000_write_word(state, 923,  in dib8000_set_agc_config()
1229 				(dib8000_read_word(state, 923) & 0xffe3) |  in dib8000_set_agc_config()
1237 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_pwm_agc_reset()  local
1238 	dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_pwm_agc_reset()
1239 …dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency /…  in dib8000_pwm_agc_reset()
1242 static int dib8000_agc_soft_split(struct dib8000_state *state)  in dib8000_agc_soft_split()  argument
1246 …if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split…  in dib8000_agc_soft_split()
1250 	agc = dib8000_read_word(state, 390);  in dib8000_agc_soft_split()
1252 	if (agc > state->current_agc->split.min_thres)  in dib8000_agc_soft_split()
1253 		split_offset = state->current_agc->split.min;  in dib8000_agc_soft_split()
1254 	else if (agc < state->current_agc->split.max_thres)  in dib8000_agc_soft_split()
1255 		split_offset = state->current_agc->split.max;  in dib8000_agc_soft_split()
1257 		split_offset = state->current_agc->split.max *  in dib8000_agc_soft_split()
1258 			(agc - state->current_agc->split.min_thres) /  in dib8000_agc_soft_split()
1259 			(state->current_agc->split.max_thres - state->current_agc->split.min_thres);  in dib8000_agc_soft_split()
1264 	dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);  in dib8000_agc_soft_split()
1270 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_agc_startup()  local
1271 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib8000_agc_startup()
1280 		if (state->revision != 0x8090)  in dib8000_agc_startup()
1281 			dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_agc_startup()
1283 			dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_agc_startup()
1285 			reg = dib8000_read_word(state, 1947)&0xff00;  in dib8000_agc_startup()
1286 			dib8000_write_word(state, 1946,  in dib8000_agc_startup()
1289 			dib8000_write_word(state, 1947, reg | (1<<14) |  in dib8000_agc_startup()
1293 			reg = dib8000_read_word(state, 1920);  in dib8000_agc_startup()
1294 			dib8000_write_word(state, 1920, (reg | 0x3) &  in dib8000_agc_startup()
1298 …if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequen…  in dib8000_agc_startup()
1300 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_agc_startup()
1310 		if (state->cfg.agc_control)  in dib8000_agc_startup()
1311 			state->cfg.agc_control(fe, 1);  in dib8000_agc_startup()
1313 		dib8000_restart_agc(state);  in dib8000_agc_startup()
1324 		if (dib8000_update_lna(state))  in dib8000_agc_startup()
1332 		dib8000_agc_soft_split(state);  in dib8000_agc_startup()
1334 		if (state->cfg.agc_control)  in dib8000_agc_startup()
1335 			state->cfg.agc_control(fe, 0);  in dib8000_agc_startup()
1340 		ret = dib8000_agc_soft_split(state);  in dib8000_agc_startup()
1347 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)  in dib8096p_host_bus_drive()  argument
1354 	reg = dib8000_read_word(state, 1798) &  in dib8096p_host_bus_drive()
1357 	dib8000_write_word(state, 1798, reg);  in dib8096p_host_bus_drive()
1360 	reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));  in dib8096p_host_bus_drive()
1362 	dib8000_write_word(state, 1799, reg);  in dib8096p_host_bus_drive()
1365 	reg = dib8000_read_word(state, 1800) &  in dib8096p_host_bus_drive()
1368 	dib8000_write_word(state, 1800, reg);  in dib8096p_host_bus_drive()
1371 	reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));  in dib8096p_host_bus_drive()
1373 	dib8000_write_word(state, 1801, reg);  in dib8096p_host_bus_drive()
1376 	reg = dib8000_read_word(state, 1802) &  in dib8096p_host_bus_drive()
1379 	dib8000_write_word(state, 1802, reg);  in dib8096p_host_bus_drive()
1401 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,  in dib8096p_cfg_DibTx()  argument
1407 	dib8000_write_word(state, 1615, 1);  in dib8096p_cfg_DibTx()
1408 	dib8000_write_word(state, 1603, P_Kin);  in dib8096p_cfg_DibTx()
1409 	dib8000_write_word(state, 1605, P_Kout);  in dib8096p_cfg_DibTx()
1410 	dib8000_write_word(state, 1606, insertExtSynchro);  in dib8096p_cfg_DibTx()
1411 	dib8000_write_word(state, 1608, synchroMode);  in dib8096p_cfg_DibTx()
1412 	dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);  in dib8096p_cfg_DibTx()
1413 	dib8000_write_word(state, 1610, syncWord & 0xffff);  in dib8096p_cfg_DibTx()
1414 	dib8000_write_word(state, 1612, syncSize);  in dib8096p_cfg_DibTx()
1415 	dib8000_write_word(state, 1615, 0);  in dib8096p_cfg_DibTx()
1418 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,  in dib8096p_cfg_DibRx()  argument
1429 		dib8000_write_word(state, 1542, syncFreq);  in dib8096p_cfg_DibRx()
1432 	dib8000_write_word(state, 1554, 1);  in dib8096p_cfg_DibRx()
1433 	dib8000_write_word(state, 1536, P_Kin);  in dib8096p_cfg_DibRx()
1434 	dib8000_write_word(state, 1537, P_Kout);  in dib8096p_cfg_DibRx()
1435 	dib8000_write_word(state, 1539, synchroMode);  in dib8096p_cfg_DibRx()
1436 	dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);  in dib8096p_cfg_DibRx()
1437 	dib8000_write_word(state, 1541, syncWord & 0xffff);  in dib8096p_cfg_DibRx()
1438 	dib8000_write_word(state, 1543, syncSize);  in dib8096p_cfg_DibRx()
1439 	dib8000_write_word(state, 1544, dataOutRate);  in dib8096p_cfg_DibRx()
1440 	dib8000_write_word(state, 1554, 0);  in dib8096p_cfg_DibRx()
1443 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)  in dib8096p_enMpegMux()  argument
1447 	reg_1287 = dib8000_read_word(state, 1287);  in dib8096p_enMpegMux()
1458 	dib8000_write_word(state, 1287, reg_1287);  in dib8096p_enMpegMux()
1461 static void dib8096p_configMpegMux(struct dib8000_state *state,  in dib8096p_configMpegMux()  argument
1468 	dib8096p_enMpegMux(state, 0);  in dib8096p_configMpegMux()
1471 	if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))  in dib8096p_configMpegMux()
1476 	dib8000_write_word(state, 1287, reg_1287);  in dib8096p_configMpegMux()
1478 	dib8096p_enMpegMux(state, 1);  in dib8096p_configMpegMux()
1481 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)  in dib8096p_setDibTxMux()  argument
1483 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);  in dib8096p_setDibTxMux()
1488 			dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);  in dib8096p_setDibTxMux()
1492 			dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);  in dib8096p_setDibTxMux()
1496 			dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);  in dib8096p_setDibTxMux()
1501 	dib8000_write_word(state, 1288, reg_1288);  in dib8096p_setDibTxMux()
1504 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)  in dib8096p_setHostBusMux()  argument
1506 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);  in dib8096p_setHostBusMux()
1511 			dib8096p_enMpegMux(state, 0);  in dib8096p_setHostBusMux()
1516 			dib8096p_enMpegMux(state, 0);  in dib8096p_setHostBusMux()
1526 	dib8000_write_word(state, 1288, reg_1288);  in dib8096p_setHostBusMux()
1531 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_set_diversity_in()  local
1539 			dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);  in dib8096p_set_diversity_in()
1543 			reg_1287 = dib8000_read_word(state, 1287);  in dib8096p_set_diversity_in()
1548 				dib8000_write_word(state, 1287, reg_1287);  in dib8096p_set_diversity_in()
1550 			state->input_mode_mpeg = 1;  in dib8096p_set_diversity_in()
1555 			dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);  in dib8096p_set_diversity_in()
1556 			state->input_mode_mpeg = 0;  in dib8096p_set_diversity_in()
1560 	dib8000_set_diversity_in(state->fe[0], onoff);  in dib8096p_set_diversity_in()
1566 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_set_output_mode()  local
1571 	state->output_mode = mode;  in dib8096p_set_output_mode()
1572 	dib8096p_host_bus_drive(state, 1);  in dib8096p_set_output_mode()
1575 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);  in dib8096p_set_output_mode()
1576 	outreg   = dib8000_read_word(state, 1286) &  in dib8096p_set_output_mode()
1587 				dib8096p_configMpegMux(state, 3, 1, 1);  in dib8096p_set_output_mode()
1588 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);  in dib8096p_set_output_mode()
1591 				dib8096p_setHostBusMux(state,  in dib8096p_set_output_mode()
1600 				dib8096p_configMpegMux(state, 2, 0, 0);  in dib8096p_set_output_mode()
1601 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);  in dib8096p_set_output_mode()
1604 				dib8096p_setHostBusMux(state,  in dib8096p_set_output_mode()
1612 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);  in dib8096p_set_output_mode()
1620 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);  in dib8096p_set_output_mode()
1628 			dib8096p_setDibTxMux(state, DIV_ON_DIBTX);  in dib8096p_set_output_mode()
1629 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8096p_set_output_mode()
1634 			dib8096p_setDibTxMux(state, ADC_ON_DIBTX);  in dib8096p_set_output_mode()
1635 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8096p_set_output_mode()
1643 			state->cfg.output_mpeg2_in_188_bytes);  in dib8096p_set_output_mode()
1644 	if (state->cfg.output_mpeg2_in_188_bytes)  in dib8096p_set_output_mode()
1647 	ret |= dib8000_write_word(state, 299, smo_mode);  in dib8096p_set_output_mode()
1649 	ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);  in dib8096p_set_output_mode()
1650 	ret |= dib8000_write_word(state, 1286, outreg);  in dib8096p_set_output_mode()
1679 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_write_serpar()  local
1685 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;  in dib8096p_tuner_write_serpar()
1690 	dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));  in dib8096p_tuner_write_serpar()
1691 	dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);  in dib8096p_tuner_write_serpar()
1699 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_read_serpar()  local
1706 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;  in dib8096p_tuner_read_serpar()
1711 	dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));  in dib8096p_tuner_read_serpar()
1715 		n_empty = dib8000_read_word(state, 1984)&0x1;  in dib8096p_tuner_read_serpar()
1721 	read_word = dib8000_read_word(state, 1987);  in dib8096p_tuner_read_serpar()
1743 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_rw_on_apb()  local
1747 		dib8000_write_word(state, apb_address,  in dib8096p_rw_on_apb()
1750 		word = dib8000_read_word(state, apb_address);  in dib8096p_rw_on_apb()
1760 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_xfer()  local
1851 			i = ((dib8000_read_word(state, 921) >> 12)&0x3);  in dib8096p_tuner_xfer()
1852 			word = dib8000_read_word(state, 924+i);  in dib8096p_tuner_xfer()
1862 				word = (dib8000_read_word(state, 921) &  in dib8096p_tuner_xfer()
1865 				dib8000_write_word(state, 921, word);  in dib8096p_tuner_xfer()
1896 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_tuner_sleep()  local
1901 	en_cur_state = dib8000_read_word(state, 1922);  in dib8096p_tuner_sleep()
1905 		state->tuner_enable = en_cur_state ;  in dib8096p_tuner_sleep()
1910 		if (state->tuner_enable != 0)  in dib8096p_tuner_sleep()
1911 			en_cur_state = state->tuner_enable;  in dib8096p_tuner_sleep()
1914 	dib8000_write_word(state, 1922, en_cur_state);  in dib8096p_tuner_sleep()
1926 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_adc_power()  local
1930 	val = dib8000_read32(state, 384);  in dib8000_get_adc_power()
1945 	struct dib8000_state *state = fe->demodulator_priv;  in dib8090p_get_dc_power()  local
1950 			val = dib8000_read_word(state, 403);  in dib8090p_get_dc_power()
1953 			val = dib8000_read_word(state, 404);  in dib8090p_get_dc_power()
1962 static void dib8000_update_timf(struct dib8000_state *state)  in dib8000_update_timf()  argument
1964 	u32 timf = state->timf = dib8000_read32(state, 435);  in dib8000_update_timf()
1966 	dib8000_write_word(state, 29, (u16) (timf >> 16));  in dib8000_update_timf()
1967 	dib8000_write_word(state, 30, (u16) (timf & 0xffff));  in dib8000_update_timf()
1968 	dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default);  in dib8000_update_timf()
1973 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_ctrl_timf()  local
1977 			state->timf = timf;  in dib8000_ctrl_timf()
1980 			dib8000_update_timf(state);  in dib8000_ctrl_timf()
1985 	dib8000_set_bandwidth(state->fe[0], 6000);  in dib8000_ctrl_timf()
1987 	return state->timf;  in dib8000_ctrl_timf()
1996 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)  in dib8000_set_layer()  argument
1999 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_layer()
2040 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment…  in dib8000_set_layer()
2061 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)  in dib8000_adp_fine_tune()  argument
2083 		dib8000_write_word(state, 215 + i, adp[i]);  in dib8000_adp_fine_tune()
2088 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)  in dib8000_update_ana_gain()  argument
2092 	dib8000_write_word(state, 116, ana_gain);  in dib8000_update_ana_gain()
2097 			dib8000_write_word(state, 80 + i, adc_target_16dB[i]);  in dib8000_update_ana_gain()
2100 			dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);  in dib8000_update_ana_gain()
2104 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)  in dib8000_load_ana_fe_coefs()  argument
2108 	if (state->isdbt_cfg_loaded == 0)  in dib8000_load_ana_fe_coefs()
2110 			dib8000_write_word(state, 117 + mode, ana_fe[mode]);  in dib8000_load_ana_fe_coefs()
2123 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)  in dib8000_get_init_prbs()  argument
2130 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {  in dib8000_get_init_prbs()
2141 static void dib8000_set_13seg_channel(struct dib8000_state *state)  in dib8000_set_13seg_channel()  argument
2146 	state->seg_mask = 0x1fff; /* All 13 segments enabled */  in dib8000_set_13seg_channel()
2149 …if (state->isdbt_cfg_loaded == 0) {  /* if not Sound Broadcasting mode : put default values for 13…  in dib8000_set_13seg_channel()
2150 		dib8000_write_word(state, 180, (16 << 6) | 9);  in dib8000_set_13seg_channel()
2151 		dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);  in dib8000_set_13seg_channel()
2154 			dib8000_write_word(state, 181+i, coff_pow);  in dib8000_set_13seg_channel()
2158 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);  in dib8000_set_13seg_channel()
2161 		dib8000_write_word(state, 340, (8 << 6) | (6 << 0));  in dib8000_set_13seg_channel()
2163 		dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));  in dib8000_set_13seg_channel()
2165 		dib8000_write_word(state, 228, 0);  /* default value */  in dib8000_set_13seg_channel()
2166 		dib8000_write_word(state, 265, 31); /* default value */  in dib8000_set_13seg_channel()
2167 		dib8000_write_word(state, 205, 0x200f); /* init value */  in dib8000_set_13seg_channel()
2175 	if (state->cfg.pll->ifreq == 0)  in dib8000_set_13seg_channel()
2176 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s…  in dib8000_set_13seg_channel()
2178 	dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);  in dib8000_set_13seg_channel()
2181 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)  in dib8000_set_subchannel_prbs()  argument
2185 	reg_1 = dib8000_read_word(state, 1);  in dib8000_set_subchannel_prbs()
2186 	dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */  in dib8000_set_subchannel_prbs()
2189 static void dib8000_small_fine_tune(struct dib8000_state *state)  in dib8000_small_fine_tune()  argument
2193 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_small_fine_tune()
2195 	dib8000_write_word(state, 352, state->seg_diff_mask);  in dib8000_small_fine_tune()
2196 	dib8000_write_word(state, 353, state->seg_mask);  in dib8000_small_fine_tune()
2199 	dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);  in dib8000_small_fine_tune()
2269 			dib8000_write_word(state, 343 + i, ncoeff[i]);  in dib8000_small_fine_tune()
2275 static void dib8000_set_sb_channel(struct dib8000_state *state)  in dib8000_set_sb_channel()  argument
2277 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_sb_channel()
2282 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */  in dib8000_set_sb_channel()
2283 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi…  in dib8000_set_sb_channel()
2285 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */  in dib8000_set_sb_channel()
2286 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = …  in dib8000_set_sb_channel()
2290 		state->seg_mask = 0x00E0;  in dib8000_set_sb_channel()
2292 		state->seg_mask = 0x0040;  in dib8000_set_sb_channel()
2294 	dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);  in dib8000_set_sb_channel()
2298 …dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partia…  in dib8000_set_sb_channel()
2300 …dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_fr…  in dib8000_set_sb_channel()
2301 …dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres…  in dib8000_set_sb_channel()
2306 		if (state->mode == 3)  in dib8000_set_sb_channel()
2307 			dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));  in dib8000_set_sb_channel()
2309 			dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));  in dib8000_set_sb_channel()
2312 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);  in dib8000_set_sb_channel()
2315 		dib8000_write_word(state, 180, 0x1fcf | (1 << 14));  in dib8000_set_sb_channel()
2317 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);  in dib8000_set_sb_channel()
2321 	dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */  in dib8000_set_sb_channel()
2322 	dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */  in dib8000_set_sb_channel()
2325 		dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */  in dib8000_set_sb_channel()
2329 		dib8000_write_word(state, 181+i, coff[i]);  in dib8000_set_sb_channel()
2330 		dib8000_write_word(state, 184+i, coff[i]);  in dib8000_set_sb_channel()
2338 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh …  in dib8000_set_sb_channel()
2341 		dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */  in dib8000_set_sb_channel()
2343 		dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */  in dib8000_set_sb_channel()
2346 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)  in dib8000_set_isdbt_common_channel()  argument
2352 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_isdbt_common_channel()
2358 	dib8000_write_word(state, 10, (seq << 4));  in dib8000_set_isdbt_common_channel()
2361 	state->mode = fft_to_mode(state);  in dib8000_set_isdbt_common_channel()
2364 	tmp = dib8000_read_word(state, 1);  in dib8000_set_isdbt_common_channel()
2365 	dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));  in dib8000_set_isdbt_common_channel()
2367 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep…  in dib8000_set_isdbt_common_channel()
2371 		state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];  in dib8000_set_isdbt_common_channel()
2375 			state->seg_diff_mask |= 1 << permu_seg[i+1];  in dib8000_set_isdbt_common_channel()
2380 			state->seg_diff_mask |= 1 << permu_seg[i];  in dib8000_set_isdbt_common_channel()
2383 	if (state->seg_diff_mask)  in dib8000_set_isdbt_common_channel()
2384 		dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);  in dib8000_set_isdbt_common_channel()
2386 		dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */  in dib8000_set_isdbt_common_channel()
2389 		max_constellation = dib8000_set_layer(state, i, max_constellation);  in dib8000_set_isdbt_common_channel()
2391 		state->layer_b_nb_seg = c->layer[1].segment_count;  in dib8000_set_isdbt_common_channel()
2392 		state->layer_c_nb_seg = c->layer[2].segment_count;  in dib8000_set_isdbt_common_channel()
2396 	dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);  in dib8000_set_isdbt_common_channel()
2398 	state->differential_constellation = (state->seg_diff_mask != 0);  in dib8000_set_isdbt_common_channel()
2401 	ana_gain = dib8000_adp_fine_tune(state, max_constellation);  in dib8000_set_isdbt_common_channel()
2404 	dib8000_update_ana_gain(state, ana_gain);  in dib8000_set_isdbt_common_channel()
2408 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);  in dib8000_set_isdbt_common_channel()
2410 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */  in dib8000_set_isdbt_common_channel()
2414 		dib8000_set_sb_channel(state);  in dib8000_set_isdbt_common_channel()
2416 			init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel);  in dib8000_set_isdbt_common_channel()
2420 		dib8000_set_13seg_channel(state);  in dib8000_set_isdbt_common_channel()
2425 	dib8000_small_fine_tune(state);  in dib8000_set_isdbt_common_channel()
2427 	dib8000_set_subchannel_prbs(state, init_prbs);  in dib8000_set_isdbt_common_channel()
2431 		if ((((~state->seg_diff_mask) >> i) & 1) == 1) {  in dib8000_set_isdbt_common_channel()
2432 …p_cfr_left_edge  += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i -…  in dib8000_set_isdbt_common_channel()
2433 …p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i …  in dib8000_set_isdbt_common_channel()
2436 	dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */  in dib8000_set_isdbt_common_channel()
2437 	dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */  in dib8000_set_isdbt_common_channel()
2440 	dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */  in dib8000_set_isdbt_common_channel()
2441 	dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */  in dib8000_set_isdbt_common_channel()
2442 	dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */  in dib8000_set_isdbt_common_channel()
2445 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_…  in dib8000_set_isdbt_common_channel()
2447 …dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be a…  in dib8000_set_isdbt_common_channel()
2449 	dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */  in dib8000_set_isdbt_common_channel()
2450 	dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */  in dib8000_set_isdbt_common_channel()
2452 	dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */  in dib8000_set_isdbt_common_channel()
2461 	dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */  in dib8000_set_isdbt_common_channel()
2462 	dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */  in dib8000_set_isdbt_common_channel()
2463 	dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */  in dib8000_set_isdbt_common_channel()
2467 	if (state->isdbt_cfg_loaded == 0)  in dib8000_set_isdbt_common_channel()
2468 		dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */  in dib8000_set_isdbt_common_channel()
2470 	state->isdbt_cfg_loaded = 0;  in dib8000_set_isdbt_common_channel()
2473 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,  in dib8000_wait_lock()  argument
2481 			if (state->revision == 0x8090)  in dib8000_wait_lock()
2489 		dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));  in dib8000_wait_lock()
2490 		dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));  in dib8000_wait_lock()
2497 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_autosearch_start()  local
2498 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_autosearch_start()
2500 	u32 value, internal = state->cfg.pll->internal;  in dib8000_autosearch_start()
2502 	if (state->revision == 0x8090)  in dib8000_autosearch_start()
2503 		internal = dib8000_read32(state, 23) / 1000;  in dib8000_autosearch_start()
2505 	if ((state->revision >= 0x8002) &&  in dib8000_autosearch_start()
2506 	    (state->autosearch_state == AS_SEARCHING_FFT)) {  in dib8000_autosearch_start()
2507 		dib8000_write_word(state,  37, 0x0065); /* P_ctrl_pha_off_max default values */  in dib8000_autosearch_start()
2508 		dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */  in dib8000_autosearch_start()
2510 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P…  in dib8000_autosearch_start()
2511 		dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */  in dib8000_autosearch_start()
2512 		dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */  in dib8000_autosearch_start()
2513 		dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */  in dib8000_autosearch_start()
2514 		dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */  in dib8000_autosearch_start()
2515 …dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P…  in dib8000_autosearch_start()
2517 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2518 …value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_se…  in dib8000_autosearch_start()
2520 …value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_se…  in dib8000_autosearch_start()
2522 		dib8000_write_word(state, 17, 0);  in dib8000_autosearch_start()
2523 		dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */  in dib8000_autosearch_start()
2524 		dib8000_write_word(state, 19, 0);  in dib8000_autosearch_start()
2525 		dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */  in dib8000_autosearch_start()
2526 		dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */  in dib8000_autosearch_start()
2527 		dib8000_write_word(state, 22, value & 0xffff);  in dib8000_autosearch_start()
2529 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2530 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha…  in dib8000_autosearch_start()
2532 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha…  in dib8000_autosearch_start()
2533 		dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */  in dib8000_autosearch_start()
2536 		dib8000_write_word(state, 356, 0);  in dib8000_autosearch_start()
2537 		dib8000_write_word(state, 357, 0x111);  in dib8000_autosearch_start()
2539 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart…  in dib8000_autosearch_start()
2540 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart…  in dib8000_autosearch_start()
2541 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_…  in dib8000_autosearch_start()
2542 	} else if ((state->revision >= 0x8002) &&  in dib8000_autosearch_start()
2543 		   (state->autosearch_state == AS_SEARCHING_GUARD)) {  in dib8000_autosearch_start()
2553 		c->transmission_mode = state->found_nfft;  in dib8000_autosearch_start()
2555 		dib8000_set_isdbt_common_channel(state, slist, 1);  in dib8000_autosearch_start()
2558 		dib8000_write_word(state, 6, 0x4);  in dib8000_autosearch_start()
2559 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2560 …dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock…  in dib8000_autosearch_start()
2562 			dib8000_write_word(state, 7, 0x8);  in dib8000_autosearch_start()
2563 		dib8000_write_word(state, 8, 0x1000);  in dib8000_autosearch_start()
2566 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2567 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2569 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2571 		dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */  in dib8000_autosearch_start()
2574 		dib8000_write_word(state, 356, 0);  in dib8000_autosearch_start()
2575 		dib8000_write_word(state, 357, 0xf);  in dib8000_autosearch_start()
2577 		value = dib8000_read_word(state, 0);  in dib8000_autosearch_start()
2578 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));  in dib8000_autosearch_start()
2579 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */  in dib8000_autosearch_start()
2580 		dib8000_write_word(state, 0, (u16)value);  in dib8000_autosearch_start()
2593 			dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  in dib8000_autosearch_start()
2600 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 t…  in dib8000_autosearch_start()
2609 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 */  in dib8000_autosearch_start()
2616 		dib8000_set_isdbt_common_channel(state, slist, 1);  in dib8000_autosearch_start()
2619 		dib8000_write_word(state, 6, 0x4);  in dib8000_autosearch_start()
2620 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2621 			dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));  in dib8000_autosearch_start()
2623 			dib8000_write_word(state, 7, 0x8);  in dib8000_autosearch_start()
2624 		dib8000_write_word(state, 8, 0x1000);  in dib8000_autosearch_start()
2627 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2628 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2630 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2632 		value = dib8000_read_word(state, 0);  in dib8000_autosearch_start()
2633 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));  in dib8000_autosearch_start()
2634 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */  in dib8000_autosearch_start()
2635 		dib8000_write_word(state, 0, (u16)value);  in dib8000_autosearch_start()
2642 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_autosearch_irq()  local
2643 	u16 irq_pending = dib8000_read_word(state, 1284);  in dib8000_autosearch_irq()
2645 	if ((state->revision >= 0x8002) &&  in dib8000_autosearch_irq()
2646 	    (state->autosearch_state == AS_SEARCHING_FFT)) {  in dib8000_autosearch_irq()
2666 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)  in dib8000_viterbi_state()  argument
2670 	tmp = dib8000_read_word(state, 771);  in dib8000_viterbi_state()
2672 		dib8000_write_word(state, 771, tmp & 0xfffd);  in dib8000_viterbi_state()
2674 		dib8000_write_word(state, 771, tmp | (1<<1));  in dib8000_viterbi_state()
2677 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)  in dib8000_set_dds()  argument
2681 	u32 dds = state->cfg.pll->ifreq & 0x1ffffff;  in dib8000_set_dds()
2682 	u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));  in dib8000_set_dds()
2685 	if (state->revision == 0x8090) {  in dib8000_set_dds()
2687 		unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);  in dib8000_set_dds()
2697 		unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);  in dib8000_set_dds()
2711 	if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {  in dib8000_set_dds()
2713 		dib8000_write_word(state, 26, invert);  in dib8000_set_dds()
2714 		dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);  in dib8000_set_dds()
2715 		dib8000_write_word(state, 28, (u16)(dds & 0xffff));  in dib8000_set_dds()
2719 static void dib8000_set_frequency_offset(struct dib8000_state *state)  in dib8000_set_frequency_offset()  argument
2721 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_frequency_offset()
2726 	if (state->fe[0]->ops.tuner_ops.get_frequency)  in dib8000_set_frequency_offset()
2727 		state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], &current_rf);  in dib8000_set_frequency_offset()
2734 		state->subchannel = c->isdbt_sb_subchannel;  in dib8000_set_frequency_offset()
2736 		i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */  in dib8000_set_frequency_offset()
2737 		dib8000_write_word(state, 26, c->inversion ^ i);  in dib8000_set_frequency_offset()
2739 		if (state->cfg.pll->ifreq == 0) { /* low if tuner */  in dib8000_set_frequency_offset()
2741 				dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);  in dib8000_set_frequency_offset()
2751 	dib8000_set_dds(state, total_dds_offset_khz);  in dib8000_set_frequency_offset()
2756 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)  in dib8000_get_symbol_duration()  argument
2758 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_get_symbol_duration()
2778 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_st…  in dib8000_set_isdbt_loop_params()  argument
2780 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_isdbt_loop_params()
2787 …reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha…  in dib8000_set_isdbt_loop_params()
2788 …reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  …  in dib8000_set_isdbt_loop_params()
2790 …reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha…  in dib8000_set_isdbt_loop_params()
2791 …reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P…  in dib8000_set_isdbt_loop_params()
2794 …reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6,…  in dib8000_set_isdbt_loop_params()
2795 …reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P…  in dib8000_set_isdbt_loop_params()
2801 …reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=…  in dib8000_set_isdbt_loop_params()
2802 					reg_37 = (12-state->mode) | ((5 + state->mode) << 5);  in dib8000_set_isdbt_loop_params()
2804 …reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=…  in dib8000_set_isdbt_loop_params()
2805 					reg_37 = (11-state->mode) | ((5 + state->mode) << 5);  in dib8000_set_isdbt_loop_params()
2808 …reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_…  in dib8000_set_isdbt_loop_params()
2809 				reg_37 = ((5+state->mode) << 5) | (10 - state->mode);  in dib8000_set_isdbt_loop_params()
2813 	dib8000_write_word(state, 32, reg_32);  in dib8000_set_isdbt_loop_params()
2814 	dib8000_write_word(state, 37, reg_37);  in dib8000_set_isdbt_loop_params()
2817 static void dib8000_demod_restart(struct dib8000_state *state)  in dib8000_demod_restart()  argument
2819 	dib8000_write_word(state, 770, 0x4000);  in dib8000_demod_restart()
2820 	dib8000_write_word(state, 770, 0x0000);  in dib8000_demod_restart()
2824 static void dib8000_set_sync_wait(struct dib8000_state *state)  in dib8000_set_sync_wait()  argument
2826 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_sync_wait()
2843 	if (state->cfg.diversity_delay == 0)  in dib8000_set_sync_wait()
2846 …sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add …  in dib8000_set_sync_wait()
2848 	dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));  in dib8000_set_sync_wait()
2851 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode …  in dib8000_get_timeout()  argument
2854 		delay *= state->symbol_duration;  in dib8000_get_timeout()
2861 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_status()  local
2862 	return state->status;  in dib8000_get_status()
2867 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_tune_state()  local
2868 	return state->tune_state;  in dib8000_get_tune_state()
2873 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_tune_state()  local
2875 	state->tune_state = tune_state;  in dib8000_set_tune_state()
2881 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_tune_restart_from_demod()  local
2883 	state->status = FE_STATUS_TUNE_PENDING;  in dib8000_tune_restart_from_demod()
2884 	state->tune_state = CT_DEMOD_START;  in dib8000_tune_restart_from_demod()
2890 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_lock()  local
2892 	if (state->revision == 0x8090)  in dib8000_read_lock()
2893 		return dib8000_read_word(state, 570);  in dib8000_read_lock()
2894 	return dib8000_read_word(state, 568);  in dib8000_read_lock()
2897 static int dib8090p_init_sdram(struct dib8000_state *state)  in dib8090p_init_sdram()  argument
2902 	reg = dib8000_read_word(state, 274) & 0xfff0;  in dib8090p_init_sdram()
2903 	dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */  in dib8090p_init_sdram()
2905 	dib8000_write_word(state, 1803, (7 << 2));  in dib8090p_init_sdram()
2907 	reg = dib8000_read_word(state, 1280);  in dib8090p_init_sdram()
2908 	dib8000_write_word(state, 1280,  reg | (1 << 2)); /* force restart P_restart_sdram */  in dib8090p_init_sdram()
2909 	dib8000_write_word(state, 1280,  reg); /* release restart P_restart_sdram */  in dib8090p_init_sdram()
3001 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_tune()  local
3002 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_tune()
3003 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib8000_tune()
3008 	unsigned long *timeout = &state->timeout;  in dib8000_tune()
3020 			state->channel_parameters_set, *tune_state, state->autosearch_state, now);  in dib8000_tune()
3027 		if (state->revision == 0x8090)  in dib8000_tune()
3028 			dib8090p_init_sdram(state);  in dib8000_tune()
3029 		state->status = FE_STATUS_TUNE_PENDING;  in dib8000_tune()
3030 		state->channel_parameters_set = is_manual_mode(c);  in dib8000_tune()
3033 			state->channel_parameters_set ? "manual" : "auto");  in dib8000_tune()
3035 		dib8000_viterbi_state(state, 0); /* force chan dec in restart */  in dib8000_tune()
3038 		dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);  in dib8000_tune()
3040 		dib8000_set_frequency_offset(state);  in dib8000_tune()
3043 		if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */  in dib8000_tune()
3045 			if (state->revision != 0x8090) {  in dib8000_tune()
3046 				state->agc1_max = dib8000_read_word(state, 108);  in dib8000_tune()
3047 				state->agc1_min = dib8000_read_word(state, 109);  in dib8000_tune()
3048 				state->agc2_max = dib8000_read_word(state, 110);  in dib8000_tune()
3049 				state->agc2_min = dib8000_read_word(state, 111);  in dib8000_tune()
3050 				agc1 = dib8000_read_word(state, 388);  in dib8000_tune()
3051 				agc2 = dib8000_read_word(state, 389);  in dib8000_tune()
3052 				dib8000_write_word(state, 108, agc1);  in dib8000_tune()
3053 				dib8000_write_word(state, 109, agc1);  in dib8000_tune()
3054 				dib8000_write_word(state, 110, agc2);  in dib8000_tune()
3055 				dib8000_write_word(state, 111, agc2);  in dib8000_tune()
3058 			state->autosearch_state = AS_SEARCHING_FFT;  in dib8000_tune()
3059 			state->found_nfft = TRANSMISSION_MODE_AUTO;  in dib8000_tune()
3060 			state->found_guard = GUARD_INTERVAL_AUTO;  in dib8000_tune()
3063 			state->autosearch_state = AS_DONE;  in dib8000_tune()
3066 		state->symbol_duration = dib8000_get_symbol_duration(state);  in dib8000_tune()
3071 		if (state->revision == 0x8090)  in dib8000_tune()
3081 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3082 			state->autosearch_state = AS_DONE;  in dib8000_tune()
3086 …state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel foun…  in dib8000_tune()
3088 			if (state->autosearch_state == AS_SEARCHING_GUARD)  in dib8000_tune()
3091 				state->autosearch_state = AS_DONE;  in dib8000_tune()
3100 		switch (state->autosearch_state) {  in dib8000_tune()
3103 			if (state->revision == 0x8090) {  in dib8000_tune()
3104 				corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));  in dib8000_tune()
3105 				corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));  in dib8000_tune()
3106 				corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));  in dib8000_tune()
3108 				corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));  in dib8000_tune()
3109 				corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));  in dib8000_tune()
3110 				corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));  in dib8000_tune()
3122 				state->found_nfft = TRANSMISSION_MODE_2K;  in dib8000_tune()
3125 				state->found_nfft = TRANSMISSION_MODE_4K;  in dib8000_tune()
3129 				state->found_nfft = TRANSMISSION_MODE_8K;  in dib8000_tune()
3135 			state->autosearch_state = AS_SEARCHING_GUARD;  in dib8000_tune()
3136 			if (state->revision == 0x8090)  in dib8000_tune()
3143 			if (state->revision == 0x8090)  in dib8000_tune()
3144 				state->found_guard = dib8000_read_word(state, 572) & 0x3;  in dib8000_tune()
3146 				state->found_guard = dib8000_read_word(state, 570) & 0x3;  in dib8000_tune()
3153 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3154 			state->autosearch_state = AS_DONE;  in dib8000_tune()
3161 		dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);  in dib8000_tune()
3162 		dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */  in dib8000_tune()
3167 		dib8000_demod_restart(state);  in dib8000_tune()
3169 		dib8000_set_sync_wait(state);  in dib8000_tune()
3170 		dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);  in dib8000_tune()
3172 		locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */  in dib8000_tune()
3174 		*timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);  in dib8000_tune()
3181 			dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */  in dib8000_tune()
3182 			if (!state->differential_constellation) {  in dib8000_tune()
3184 …*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEP…  in dib8000_tune()
3195 		if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {  in dib8000_tune()
3197 …if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input…  in dib8000_tune()
3199 …else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input faill…  in dib8000_tune()
3201 				dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3202 				dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3203 				state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3206 			dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3207 			dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3209 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3223 		dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3224 		dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3229 		    && !state->differential_constellation) {  in dib8000_tune()
3230 			state->subchannel = 0;  in dib8000_tune()
3234 			state->status = FE_STATUS_LOCKED;  in dib8000_tune()
3239 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable …  in dib8000_tune()
3246 						state->longest_intlv_layer = i;  in dib8000_tune()
3258 			if (state->diversity_onoff != 0) /* because of diversity sync */  in dib8000_tune()
3263 				deeper_interleaver, state->longest_intlv_layer, locks, *timeout);  in dib8000_tune()
3272 		if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */  in dib8000_tune()
3279 			    && !state->differential_constellation)  in dib8000_tune()
3281 				state->status = FE_STATUS_DEMOD_SUCCESS;  in dib8000_tune()
3283 				state->status = FE_STATUS_DATA_LOCKED;  in dib8000_tune()
3288 			    && !state->differential_constellation) { /* continue to try init prbs autosearch */  in dib8000_tune()
3289 				state->subchannel += 3;  in dib8000_tune()
3299 					state->status = FE_STATUS_DATA_LOCKED;  in dib8000_tune()
3301 					state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3308 		if (state->subchannel <= 41) {  in dib8000_tune()
3309 			dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel));  in dib8000_tune()
3313 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3325 		if ((state->revision != 0x8090) && (state->agc1_max != 0)) {  in dib8000_tune()
3326 			dib8000_write_word(state, 108, state->agc1_max);  in dib8000_tune()
3327 			dib8000_write_word(state, 109, state->agc1_min);  in dib8000_tune()
3328 			dib8000_write_word(state, 110, state->agc2_max);  in dib8000_tune()
3329 			dib8000_write_word(state, 111, state->agc2_min);  in dib8000_tune()
3330 			state->agc1_max = 0;  in dib8000_tune()
3331 			state->agc1_min = 0;  in dib8000_tune()
3332 			state->agc2_max = 0;  in dib8000_tune()
3333 			state->agc2_min = 0;  in dib8000_tune()
3343 		return ret * state->symbol_duration;  in dib8000_tune()
3344 	if ((ret > 0) && (ret < state->symbol_duration))  in dib8000_tune()
3345 		return state->symbol_duration; /* at least one symbol */  in dib8000_tune()
3351 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_wakeup()  local
3355 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_wakeup()
3356 	dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_wakeup()
3357 	if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)  in dib8000_wakeup()
3360 	if (state->revision == 0x8090)  in dib8000_wakeup()
3361 		dib8000_sad_calib(state);  in dib8000_wakeup()
3363 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_wakeup()
3364 		ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);  in dib8000_wakeup()
3374 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_sleep()  local
3378 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_sleep()
3379 		ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);  in dib8000_sleep()
3384 	if (state->revision != 0x8090)  in dib8000_sleep()
3386 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);  in dib8000_sleep()
3387 …return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_A…  in dib8000_sleep()
3395 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_frontend()  local
3412 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_get_frontend()
3413 		state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);  in dib8000_get_frontend()
3417 			state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c);  in dib8000_get_frontend()
3418 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde…  in dib8000_get_frontend()
3420 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_p…  in dib8000_get_frontend()
3421 …state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_prope…  in dib8000_get_frontend()
3422 …state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->d…  in dib8000_get_frontend()
3423 …state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_…  in dib8000_get_frontend()
3424 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_fronte…  in dib8000_get_frontend()
3426 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_fronten…  in dib8000_get_frontend()
3427 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend…  in dib8000_get_frontend()
3428 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_pr…  in dib8000_get_frontend()
3429 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]-…  in dib8000_get_frontend()
3437 	c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;  in dib8000_get_frontend()
3439 	if (state->revision == 0x8090)  in dib8000_get_frontend()
3440 		val = dib8000_read_word(state, 572);  in dib8000_get_frontend()
3442 		val = dib8000_read_word(state, 570);  in dib8000_get_frontend()
3479 	val = dib8000_read_word(state, 505);  in dib8000_get_frontend()
3486 		val = dib8000_read_word(state, 493 + i) & 0x0f;  in dib8000_get_frontend()
3498 		val = dib8000_read_word(state, 499 + i) & 0x3;  in dib8000_get_frontend()
3507 		val = dib8000_read_word(state, 481 + i);  in dib8000_get_frontend()
3536 		val = dib8000_read_word(state, 487 + i);  in dib8000_get_frontend()
3563 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_get_frontend()
3564 		state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode;  in dib8000_get_frontend()
3565 		state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion;  in dib8000_get_frontend()
3566 		state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode;  in dib8000_get_frontend()
3567 		state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval;  in dib8000_get_frontend()
3568 …state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception;  in dib8000_get_frontend()
3570 			state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count;  in dib8000_get_frontend()
3571 			state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving;  in dib8000_get_frontend()
3572 			state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec;  in dib8000_get_frontend()
3573 			state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation;  in dib8000_get_frontend()
3581 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_frontend()  local
3582 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_frontend()
3597 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3599 		state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;  in dib8000_set_frontend()
3600 …memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_…  in dib8000_set_frontend()
3603 		if (state->revision != 0x8090) {  in dib8000_set_frontend()
3604 			dib8000_set_diversity_in(state->fe[index_frontend], 1);  in dib8000_set_frontend()
3606 				dib8000_set_output_mode(state->fe[index_frontend],  in dib8000_set_frontend()
3609 				dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);  in dib8000_set_frontend()
3611 			dib8096p_set_diversity_in(state->fe[index_frontend], 1);  in dib8000_set_frontend()
3613 				dib8096p_set_output_mode(state->fe[index_frontend],  in dib8000_set_frontend()
3616 				dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);  in dib8000_set_frontend()
3620 		if (state->fe[index_frontend]->ops.tuner_ops.set_params)  in dib8000_set_frontend()
3621 			state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);  in dib8000_set_frontend()
3623 		dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);  in dib8000_set_frontend()
3627 	if (state->revision != 0x8090)  in dib8000_set_frontend()
3628 		dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);  in dib8000_set_frontend()
3630 		dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);  in dib8000_set_frontend()
3634 		time = dib8000_agc_startup(state->fe[0]);  in dib8000_set_frontend()
3635 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3636 			time_slave = dib8000_agc_startup(state->fe[index_frontend]);  in dib8000_set_frontend()
3656 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3657 			if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {  in dib8000_set_frontend()
3664 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3665 		dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);  in dib8000_set_frontend()
3670 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3671 			delay = dib8000_tune(state->fe[index_frontend]);  in dib8000_set_frontend()
3679 			if (state->channel_parameters_set == 0) { /* searching */  in dib8000_set_frontend()
3680 …if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_sta…  in dib8000_set_frontend()
3682 …dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the fro…  in dib8000_set_frontend()
3683 					state->channel_parameters_set = 1;  in dib8000_set_frontend()
3685 					for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {  in dib8000_set_frontend()
3688 							dib8000_tune_restart_from_demod(state->fe[l]);  in dib8000_set_frontend()
3690 …state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isd…  in dib8000_set_frontend()
3691 …state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversi…  in dib8000_set_frontend()
3692 …state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache…  in dib8000_set_frontend()
3693 …state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.gu…  in dib8000_set_frontend()
3694 …state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property…  in dib8000_set_frontend()
3696 …state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_…  in dib8000_set_frontend()
3697 …state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_c…  in dib8000_set_frontend()
3698 …state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.laye…  in dib8000_set_frontend()
3699 …state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cac…  in dib8000_set_frontend()
3708 		if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||  in dib8000_set_frontend()
3709 				dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||  in dib8000_set_frontend()
3710 				dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {  in dib8000_set_frontend()
3713 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3714 				if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)  in dib8000_set_frontend()
3718 				dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0]));  in dib8000_set_frontend()
3731 	if (state->revision != 0x8090)  in dib8000_set_frontend()
3732 		dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);  in dib8000_set_frontend()
3734 		dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);  in dib8000_set_frontend()
3735 		if (state->cfg.enMpegOutput == 0) {  in dib8000_set_frontend()
3736 			dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);  in dib8000_set_frontend()
3737 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8000_set_frontend()
3748 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_status()  local
3753 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_status()
3754 		lock_slave |= dib8000_read_lock(state->fe[index_frontend]);  in dib8000_read_status()
3771 		lock = dib8000_read_word(state, 554); /* Viterbi Layer A */  in dib8000_read_status()
3775 		lock = dib8000_read_word(state, 555); /* Viterbi Layer B */  in dib8000_read_status()
3779 		lock = dib8000_read_word(state, 556); /* Viterbi Layer C */  in dib8000_read_status()
3790 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_ber()  local
3793 	if (state->revision == 0x8090)  in dib8000_read_ber()
3794 		*ber = (dib8000_read_word(state, 562) << 16) |  in dib8000_read_ber()
3795 			dib8000_read_word(state, 563);  in dib8000_read_ber()
3797 		*ber = (dib8000_read_word(state, 560) << 16) |  in dib8000_read_ber()
3798 			dib8000_read_word(state, 561);  in dib8000_read_ber()
3804 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_unc_blocks()  local
3807 	if (state->revision == 0x8090)  in dib8000_read_unc_blocks()
3808 		*unc = dib8000_read_word(state, 567);  in dib8000_read_unc_blocks()
3810 		*unc = dib8000_read_word(state, 565);  in dib8000_read_unc_blocks()
3816 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_signal_strength()  local
3821 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_signal_strength()
3822 		state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);  in dib8000_read_signal_strength()
3829 	val = 65535 - dib8000_read_word(state, 390);  in dib8000_read_signal_strength()
3839 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_snr()  local
3843 	if (state->revision != 0x8090)  in dib8000_get_snr()
3844 		val = dib8000_read_word(state, 542);  in dib8000_get_snr()
3846 		val = dib8000_read_word(state, 544);  in dib8000_get_snr()
3853 	if (state->revision != 0x8090)  in dib8000_get_snr()
3854 		val = dib8000_read_word(state, 543);  in dib8000_get_snr()
3856 		val = dib8000_read_word(state, 545);  in dib8000_get_snr()
3872 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_snr()  local
3877 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_snr()
3878 		snr_master += dib8000_get_snr(state->fe[index_frontend]);  in dib8000_read_snr()
3988 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_time_us()  local
3989 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_get_time_us()
4102 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_stats()  local
4103 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_get_stats()
4135 	if (time_after(jiffies, state->per_jiffies_stats)) {  in dib8000_get_stats()
4136 		state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);  in dib8000_get_stats()
4141 			if (state->fe[i])  in dib8000_get_stats()
4142 				snr += dib8000_get_snr(state->fe[i]);  in dib8000_get_stats()
4157 		if (val < state->init_ucb)  in dib8000_get_stats()
4158 			state->init_ucb += 0x100000000LL;  in dib8000_get_stats()
4161 		c->block_error.stat[0].uvalue = val + state->init_ucb;  in dib8000_get_stats()
4178 	if (time_after(jiffies, state->ber_jiffies_stats)) {  in dib8000_get_stats()
4180 		state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);  in dib8000_get_stats()
4192 	if (state->revision < 0x8002)  in dib8000_get_stats()
4207 		if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {  in dib8000_get_stats()
4210 			state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);  in dib8000_get_stats()
4214 			val = dib8000_read_word(state, per_layer_regs[i].ber);  in dib8000_get_stats()
4223 			val = dib8000_read_word(state, per_layer_regs[i].per);  in dib8000_get_stats()
4243 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_slave_frontend()  local
4246 	while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))  in dib8000_set_slave_frontend()
4250 		state->fe[index_frontend] = fe_slave;  in dib8000_set_slave_frontend()
4260 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_slave_frontend()  local
4264 	return state->fe[slave_index];  in dib8000_get_slave_frontend()
4422 	struct dib8000_state *state;  in dib8000_init()  local
4426 	state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);  in dib8000_init()
4427 	if (state == NULL)  in dib8000_init()
4433 	memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));  in dib8000_init()
4434 	state->i2c.adap = i2c_adap;  in dib8000_init()
4435 	state->i2c.addr = i2c_addr;  in dib8000_init()
4436 	state->i2c.i2c_write_buffer = state->i2c_write_buffer;  in dib8000_init()
4437 	state->i2c.i2c_read_buffer = state->i2c_read_buffer;  in dib8000_init()
4438 	mutex_init(&state->i2c_buffer_lock);  in dib8000_init()
4439 	state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;  in dib8000_init()
4440 	state->gpio_val = cfg->gpio_val;  in dib8000_init()
4441 	state->gpio_dir = cfg->gpio_dir;  in dib8000_init()
4446 …if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_P…  in dib8000_init()
4447 		state->cfg.output_mode = OUTMODE_MPEG2_FIFO;  in dib8000_init()
4449 	state->fe[0] = fe;  in dib8000_init()
4450 	fe->demodulator_priv = state;  in dib8000_init()
4451 	memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));  in dib8000_init()
4453 	state->timf_default = cfg->pll->timf;  in dib8000_init()
4455 	if (dib8000_identify(&state->i2c) == 0)  in dib8000_init()
4458 	dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);  in dib8000_init()
4461 	strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",  in dib8000_init()
4462 			sizeof(state->dib8096p_tuner_adap.name));  in dib8000_init()
4463 	state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;  in dib8000_init()
4464 	state->dib8096p_tuner_adap.algo_data = NULL;  in dib8000_init()
4465 	state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;  in dib8000_init()
4466 	i2c_set_adapdata(&state->dib8096p_tuner_adap, state);  in dib8000_init()
4467 	i2c_add_adapter(&state->dib8096p_tuner_adap);  in dib8000_init()
4471 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));	/* ber_rs_len …  in dib8000_init()
4472 	state->current_demod_bw = 6000;  in dib8000_init()
4477 	kfree(state);  in dib8000_init()