Lines Matching refs:dib0090_write_reg
244 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) in dib0090_write_reg() function
335 dib0090_write_reg(state, r++, *b++); in dib0090_write_regs()
527 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_reset_digital()
531 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remai… in dib0090_reset_digital()
533 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <… in dib0090_reset_digital()
535 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
538 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
550 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
554 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
558 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
562 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
579 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
584 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
668 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_wakeup()
684 dib0090_write_reg(state, 0x04, 0); in dib0090_dcc_freq()
686 dib0090_write_reg(state, 0x04, 1); in dib0090_dcc_freq()
1027 dib0090_write_reg(state, gain_reg_addr[i], v); in dib0090_gain_apply()
1047 dib0090_write_reg(state, 0x2a, 0xffff); in dib0090_set_rframp_pwm()
1067 dib0090_write_reg(state, 0x33, 0xffff); in dib0090_set_bbramp_pwm()
1134 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); in dib0090_pwm_gain_reset()
1138 dib0090_write_reg(state, 0x04, 3); in dib0090_pwm_gain_reset()
1140 dib0090_write_reg(state, 0x04, 1); in dib0090_pwm_gain_reset()
1141 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ in dib0090_pwm_gain_reset()
1150 dib0090_write_reg(state, 0x04, DC_servo_cutoff); in dib0090_set_dc_servo()
1174 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1202 dib0090_write_reg(state, 0x32, 0); in dib0090_gain_control()
1203 dib0090_write_reg(state, 0x39, 0); in dib0090_gain_control()
1292 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : nar… in dib0090_gain_control()
1293 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1297 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); in dib0090_gain_control()
1298 …dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_gain_control()
1364 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_get_wbd_target()
1390 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) in dib0090_set_switch()
1401 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) in dib0090_set_vga()
1499 dib0090_write_reg(state, r, pgm_read_word(n++)); in dib0090_set_default_config()
1525 dib0090_write_reg(state, 0x22, 0x10); in dib0090_set_EFUSE()
1551 dib0090_write_reg(state, 0x13, (h << 10)); in dib0090_set_EFUSE()
1553 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ in dib0090_set_EFUSE()
1572 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1574 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1580 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ in dib0090_reset()
1591 dib0090_write_reg(state, 0x14, in dib0090_reset()
1594 dib0090_write_reg(state, 0x14, 1); in dib0090_reset()
1596 dib0090_write_reg(state, 0x14, 2); in dib0090_reset()
1613 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_get_offset()
1621 dib0090_write_reg(state, 0x1f, 0x4); in dib0090_get_offset()
1679 dib0090_write_reg(state, state->dc->addr, *val); in dib0090_set_trim()
1697 dib0090_write_reg(state, 0x24, reg); in dib0090_dc_offset_calibration()
1700 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); in dib0090_dc_offset_calibration()
1701 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_dc_offset_calibration()
1712 dib0090_write_reg(state, 0x01, state->dc->bb1); in dib0090_dc_offset_calibration()
1713 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); in dib0090_dc_offset_calibration()
1775 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); in dib0090_dc_offset_calibration()
1776 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_dc_offset_calibration()
1810 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); in dib0090_wbd_calibration()
1812 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); in dib0090_wbd_calibration()
1846 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ in dib0090_set_bandwidth()
1848 …dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte… in dib0090_set_bandwidth()
1849 …dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_set_bandwidth()
1851 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n… in dib0090_set_bandwidth()
1853 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ in dib0090_set_bandwidth()
1854 …dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias… in dib0090_set_bandwidth()
2076 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) in dib0090_update_tuning_table_7090()
2078 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) in dib0090_update_tuning_table_7090()
2100 dib0090_write_reg(state, 0x10, 0x2B1); in dib0090_captrim_search()
2101 dib0090_write_reg(state, 0x1e, 0x0032); in dib0090_captrim_search()
2123 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); in dib0090_captrim_search()
2128 dib0090_write_reg(state, 0x18, lo4 | state->captrim); in dib0090_captrim_search()
2137 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); in dib0090_captrim_search()
2178 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); in dib0090_captrim_search()
2198 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); in dib0090_get_temperature()
2201 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); in dib0090_get_temperature()
2209 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); in dib0090_get_temperature()
2223 dib0090_write_reg(state, 0x13, state->bias); in dib0090_get_temperature()
2224 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ in dib0090_get_temperature()
2229 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_get_temperature()
2262 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_tune()
2266 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_tune()
2285 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); in dib0090_tune()
2372 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); in dib0090_tune()
2441 dib0090_write_reg(state, 0x15, (u16) FBDiv); in dib0090_tune()
2443 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); in dib0090_tune()
2445 dib0090_write_reg(state, 0x16, (Den << 8) | 1); in dib0090_tune()
2446 dib0090_write_reg(state, 0x17, (u16) Rest); in dib0090_tune()
2447 dib0090_write_reg(state, 0x19, lo5); in dib0090_tune()
2448 dib0090_write_reg(state, 0x1c, lo6); in dib0090_tune()
2454 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); in dib0090_tune()
2471 dib0090_write_reg(state, 0x1e, 0x07ff); in dib0090_tune()
2489 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_tune()
2493 dib0090_write_reg(state, 0x09, tune->lna_bias); in dib0090_tune()
2494 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); in dib0090_tune()
2496 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); in dib0090_tune()
2498 dib0090_write_reg(state, 0x0c, tune->v2i); in dib0090_tune()
2499 dib0090_write_reg(state, 0x0d, tune->mix); in dib0090_tune()
2500 dib0090_write_reg(state, 0x0e, tune->load); in dib0090_tune()