524 	u16 PllCfg, i, v;  in dib0090_reset_digital()  local
542 	PllCfg = dib0090_read_reg(state, 0x21);  in dib0090_reset_digital()
545 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_reset_digital()
549 		PllCfg |= (1 << 15);  in dib0090_reset_digital()
550 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
553 		PllCfg &= ~(1 << 13);  in dib0090_reset_digital()
554 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
557 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_reset_digital()
558 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
561 		PllCfg |= (1 << 13);  in dib0090_reset_digital()
562 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
578 		PllCfg &= ~(1 << 15);  in dib0090_reset_digital()
579 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
583 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_reset_digital()
584 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
591 	u16 PllCfg;  in dib0090_fw_reset_digital()  local
614 	PllCfg = dib0090_fw_read_reg(state, 0x21);  in dib0090_fw_reset_digital()
617 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_fw_reset_digital()
620 		PllCfg |= (1 << 15);  in dib0090_fw_reset_digital()
621 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
624 		PllCfg &= ~(1 << 13);  in dib0090_fw_reset_digital()
625 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
628 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_fw_reset_digital()
629 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
632 		PllCfg |= (1 << 13);  in dib0090_fw_reset_digital()
633 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
649 		PllCfg &= ~(1 << 15);  in dib0090_fw_reset_digital()
650 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
654 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_fw_reset_digital()
655 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()