73 	struct stm32_ipcc *ipcc = data;  in stm32_ipcc_rx_irq()  local
74 	struct device *dev = ipcc->controller.dev;  in stm32_ipcc_rx_irq()
80 	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;  in stm32_ipcc_rx_irq()
81 	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);  in stm32_ipcc_rx_irq()
82 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_rx_irq()
87 	for (chan = 0; chan < ipcc->n_chans; chan++) {  in stm32_ipcc_rx_irq()
93 		mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);  in stm32_ipcc_rx_irq()
95 		stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,  in stm32_ipcc_rx_irq()
106 	struct stm32_ipcc *ipcc = data;  in stm32_ipcc_tx_irq()  local
107 	struct device *dev = ipcc->controller.dev;  in stm32_ipcc_tx_irq()
111 	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);  in stm32_ipcc_tx_irq()
112 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_tx_irq()
117 	for (chan = 0; chan < ipcc->n_chans ; chan++) {  in stm32_ipcc_tx_irq()
124 		stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_tx_irq()
127 		mbox_chan_txdone(&ipcc->controller.chans[chan], 0);  in stm32_ipcc_tx_irq()
138 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_send_data()  local
141 	dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);  in stm32_ipcc_send_data()
144 	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));  in stm32_ipcc_send_data()
147 	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));  in stm32_ipcc_send_data()
155 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_startup()  local
159 	ret = clk_prepare_enable(ipcc->clk);  in stm32_ipcc_startup()
161 		dev_err(ipcc->controller.dev, "can not enable the clock\n");  in stm32_ipcc_startup()
166 	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));  in stm32_ipcc_startup()
174 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_shutdown()  local
178 	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_shutdown()
181 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_shutdown()
194 	struct stm32_ipcc *ipcc;  in stm32_ipcc_probe()  local
207 	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);  in stm32_ipcc_probe()
208 	if (!ipcc)  in stm32_ipcc_probe()
212 	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {  in stm32_ipcc_probe()
217 	if (ipcc->proc_id >= STM32_MAX_PROCS) {  in stm32_ipcc_probe()
218 		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);  in stm32_ipcc_probe()
224 	ipcc->reg_base = devm_ioremap_resource(dev, res);  in stm32_ipcc_probe()
225 	if (IS_ERR(ipcc->reg_base))  in stm32_ipcc_probe()
226 		return PTR_ERR(ipcc->reg_base);  in stm32_ipcc_probe()
228 	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;  in stm32_ipcc_probe()
231 	ipcc->clk = devm_clk_get(dev, NULL);  in stm32_ipcc_probe()
232 	if (IS_ERR(ipcc->clk))  in stm32_ipcc_probe()
233 		return PTR_ERR(ipcc->clk);  in stm32_ipcc_probe()
235 	ret = clk_prepare_enable(ipcc->clk);  in stm32_ipcc_probe()
243 		ipcc->irqs[i] = of_irq_get_byname(dev->of_node, irq_name[i]);  in stm32_ipcc_probe()
244 		if (ipcc->irqs[i] < 0) {  in stm32_ipcc_probe()
246 			ret = ipcc->irqs[i];  in stm32_ipcc_probe()
250 		ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,  in stm32_ipcc_probe()
252 						dev_name(dev), ipcc);  in stm32_ipcc_probe()
260 	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_probe()
262 	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);  in stm32_ipcc_probe()
266 		ipcc->wkp = of_irq_get_byname(dev->of_node, "wakeup");  in stm32_ipcc_probe()
267 		if (ipcc->wkp < 0) {  in stm32_ipcc_probe()
269 			ret = ipcc->wkp;  in stm32_ipcc_probe()
274 		ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);  in stm32_ipcc_probe()
284 	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);  in stm32_ipcc_probe()
285 	ipcc->n_chans &= IPCFGR_CHAN_MASK;  in stm32_ipcc_probe()
287 	ipcc->controller.dev = dev;  in stm32_ipcc_probe()
288 	ipcc->controller.txdone_irq = true;  in stm32_ipcc_probe()
289 	ipcc->controller.ops = &stm32_ipcc_ops;  in stm32_ipcc_probe()
290 	ipcc->controller.num_chans = ipcc->n_chans;  in stm32_ipcc_probe()
291 	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,  in stm32_ipcc_probe()
292 					      sizeof(*ipcc->controller.chans),  in stm32_ipcc_probe()
294 	if (!ipcc->controller.chans) {  in stm32_ipcc_probe()
299 	for (i = 0; i < ipcc->controller.num_chans; i++)  in stm32_ipcc_probe()
300 		ipcc->controller.chans[i].con_priv = (void *)i;  in stm32_ipcc_probe()
302 	ret = mbox_controller_register(&ipcc->controller);  in stm32_ipcc_probe()
306 	platform_set_drvdata(pdev, ipcc);  in stm32_ipcc_probe()
308 	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);  in stm32_ipcc_probe()
313 		 ipcc->controller.num_chans, ipcc->proc_id);  in stm32_ipcc_probe()
315 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_probe()
319 	if (ipcc->wkp)  in stm32_ipcc_probe()
324 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_probe()
330 	struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);  in stm32_ipcc_remove()  local
332 	mbox_controller_unregister(&ipcc->controller);  in stm32_ipcc_remove()
334 	if (ipcc->wkp)  in stm32_ipcc_remove()
345 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);  in stm32_ipcc_set_irq_wake()  local
350 			irq_set_irq_wake(ipcc->irqs[i], enable);  in stm32_ipcc_set_irq_wake()
355 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);  in stm32_ipcc_suspend()  local
357 	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_suspend()
358 	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);  in stm32_ipcc_suspend()
367 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);  in stm32_ipcc_resume()  local
371 	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_resume()
372 	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);  in stm32_ipcc_resume()