128 	u8				cbndx;  member
225 	u8				cbndx;  member
428 	void __iomem *base = ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx);  in arm_smmu_tlb_sync_context()
448 	void __iomem *base = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);  in arm_smmu_tlb_inv_context_s1()
470 	void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);  in arm_smmu_tlb_inv_range_nosync()
544 	cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_context_fault()
555 			    fsr, iova, fsynr, cfg->cbndx);  in arm_smmu_context_fault()
589 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in arm_smmu_init_context_bank()
842 	cfg->cbndx = ret;  in arm_smmu_init_domain_context()
847 		cfg->irptndx = cfg->cbndx;  in arm_smmu_init_domain_context()
851 		cfg->vmid = cfg->cbndx + 1 + smmu->cavium_id_base;  in arm_smmu_init_domain_context()
853 		cfg->asid = cfg->cbndx + smmu->cavium_id_base;  in arm_smmu_init_domain_context()
880 	arm_smmu_write_context_bank(smmu, cfg->cbndx);  in arm_smmu_init_domain_context()
922 	smmu->cbs[cfg->cbndx].cfg = NULL;  in arm_smmu_destroy_domain_context()
923 	arm_smmu_write_context_bank(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
931 	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);  in arm_smmu_destroy_domain_context()
990 		  (s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |  in arm_smmu_write_s2cr()
1169 	u8 cbndx = smmu_domain->cfg.cbndx;  in arm_smmu_domain_add_master()  local
1179 		if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)  in arm_smmu_domain_add_master()
1184 		s2cr[idx].cbndx = cbndx;  in arm_smmu_domain_add_master()
1276 	cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_iova_to_phys_hard()