297 #define ARM_SMMU_TCR2CD(tcr, fld)	FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \
783 	cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);  in arm_smmu_cmdq_build_cmd()
790 		cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid);  in arm_smmu_cmdq_build_cmd()
791 		cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent->prefetch.size);  in arm_smmu_cmdq_build_cmd()
795 		cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);  in arm_smmu_cmdq_build_cmd()
796 		cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);  in arm_smmu_cmdq_build_cmd()
800 		cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);  in arm_smmu_cmdq_build_cmd()
803 		cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);  in arm_smmu_cmdq_build_cmd()
804 		cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);  in arm_smmu_cmdq_build_cmd()
808 		cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);  in arm_smmu_cmdq_build_cmd()
809 		cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);  in arm_smmu_cmdq_build_cmd()
813 		cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);  in arm_smmu_cmdq_build_cmd()
816 		cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);  in arm_smmu_cmdq_build_cmd()
819 		cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);  in arm_smmu_cmdq_build_cmd()
820 		cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid);  in arm_smmu_cmdq_build_cmd()
821 		cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid);  in arm_smmu_cmdq_build_cmd()
822 		cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid);  in arm_smmu_cmdq_build_cmd()
831 		cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp);  in arm_smmu_cmdq_build_cmd()
835 			cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);  in arm_smmu_cmdq_build_cmd()
837 			cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV);  in arm_smmu_cmdq_build_cmd()
838 		cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH);  in arm_smmu_cmdq_build_cmd()
839 		cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB);  in arm_smmu_cmdq_build_cmd()
840 		cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIDATA, ent->sync.msidata);  in arm_smmu_cmdq_build_cmd()
1028 	      CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cfg->cd.asid) |  in arm_smmu_write_ctx_desc()
1049 	val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span);  in arm_smmu_write_strtab_l1_desc()
1119 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);  in arm_smmu_write_strtab_ent()
1121 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);  in arm_smmu_write_strtab_ent()
1124 		dst[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,  in arm_smmu_write_strtab_ent()
1139 			 FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |  in arm_smmu_write_strtab_ent()
1140 			 FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |  in arm_smmu_write_strtab_ent()
1141 			 FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |  in arm_smmu_write_strtab_ent()
1143 			 FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_TRANS) |  in arm_smmu_write_strtab_ent()
1145 			 FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1));  in arm_smmu_write_strtab_ent()
1152 			FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS);  in arm_smmu_write_strtab_ent()
1158 			 FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) |  in arm_smmu_write_strtab_ent()
1159 			 FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) |  in arm_smmu_write_strtab_ent()
1168 		val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);  in arm_smmu_write_strtab_ent()
2038 	q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->max_n_shift);  in arm_smmu_init_one_queue()
2120 	reg  = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_2LVL);  in arm_smmu_init_strtab_2lvl()
2121 	reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, size);  in arm_smmu_init_strtab_2lvl()
2122 	reg |= FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT);  in arm_smmu_init_strtab_2lvl()
2148 	reg  = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_LINEAR);  in arm_smmu_init_strtab_linear()
2149 	reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);  in arm_smmu_init_strtab_linear()
2415 	reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |  in arm_smmu_device_reset()
2416 	      FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |  in arm_smmu_device_reset()
2417 	      FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |  in arm_smmu_device_reset()
2418 	      FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |  in arm_smmu_device_reset()
2419 	      FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |  in arm_smmu_device_reset()
2420 	      FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);  in arm_smmu_device_reset()