298 					FIELD_GET(ARM64_TCR_##fld, tcr))
862 	u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons);  in arm_smmu_cmdq_skip_err()
1098 		switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {  in arm_smmu_write_strtab_ent()
1229 			u8 id = FIELD_GET(EVTQ_0_ID, evt[0]);  in arm_smmu_evtq_thread()
1257 	sid = FIELD_GET(PRIQ_0_SID, evt[0]);  in arm_smmu_handle_ppr()
1258 	ssv = FIELD_GET(PRIQ_0_SSID_V, evt[0]);  in arm_smmu_handle_ppr()
1259 	ssid = ssv ? FIELD_GET(PRIQ_0_SSID, evt[0]) : 0;  in arm_smmu_handle_ppr()
1260 	last = FIELD_GET(PRIQ_0_PRG_LAST, evt[0]);  in arm_smmu_handle_ppr()
1261 	grpid = FIELD_GET(PRIQ_1_PRG_IDX, evt[1]);  in arm_smmu_handle_ppr()
2528 	if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL)  in arm_smmu_device_hw_probe()
2539 	switch (FIELD_GET(IDR0_TTENDIAN, reg)) {  in arm_smmu_device_hw_probe()
2581 	switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {  in arm_smmu_device_hw_probe()
2601 	switch (FIELD_GET(IDR0_TTF, reg)) {  in arm_smmu_device_hw_probe()
2625 					 FIELD_GET(IDR1_CMDQS, reg));  in arm_smmu_device_hw_probe()
2633 					 FIELD_GET(IDR1_EVTQS, reg));  in arm_smmu_device_hw_probe()
2635 					 FIELD_GET(IDR1_PRIQS, reg));  in arm_smmu_device_hw_probe()
2638 	smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg);  in arm_smmu_device_hw_probe()
2639 	smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg);  in arm_smmu_device_hw_probe()
2652 	smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg);  in arm_smmu_device_hw_probe()
2663 	if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT)  in arm_smmu_device_hw_probe()
2667 	switch (FIELD_GET(IDR5_OAS, reg)) {  in arm_smmu_device_hw_probe()