Lines Matching refs:SYM_MASK
177 #define SYM_MASK(regname, fldname) ((u64) \ macro
189 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
190 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
191 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
192 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
193 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
195 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
214 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
215 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
216 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
217 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
706 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
708 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
710 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
712 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
714 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
716 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
718 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
720 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
722 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
724 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
726 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
728 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
730 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
732 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
734 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
736 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
738 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
740 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
945 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
946 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
1150 SYM_MASK(EXTStatus, MemBISTDisabled)
1152 SYM_MASK(EXTStatus, MemBISTEndTest)
1166 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1167 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1168 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1169 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1170 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1171 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1172 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1178 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1182 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1184 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1185 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1192 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1193 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1194 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1195 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1196 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1200 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1202 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1224 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1226 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1253 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1297 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1319 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1471 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); in qib_7322_sdma_sendctrl()
1473 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); in qib_7322_sdma_sendctrl()
1476 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); in qib_7322_sdma_sendctrl()
1478 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); in qib_7322_sdma_sendctrl()
1481 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); in qib_7322_sdma_sendctrl()
1483 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); in qib_7322_sdma_sendctrl()
1486 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | in qib_7322_sdma_sendctrl()
1487 SYM_MASK(SendCtrl_0, TxeAbortIbc) | in qib_7322_sdma_sendctrl()
1488 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); in qib_7322_sdma_sendctrl()
1490 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | in qib_7322_sdma_sendctrl()
1491 SYM_MASK(SendCtrl_0, TxeAbortIbc) | in qib_7322_sdma_sendctrl()
1492 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); in qib_7322_sdma_sendctrl()
1498 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1509 SYM_MASK(SendCtrl_0, SDmaCleanup)); in qib_7322_sdma_sendctrl()
1515 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1802 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { in handle_serdes_issues()
1808 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && in handle_serdes_issues()
1964 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { in handle_7322_p_errors()
1971 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in handle_7322_p_errors()
1978 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? in handle_7322_p_errors()
1980 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, in handle_7322_p_errors()
1982 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? in handle_7322_p_errors()
2129 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { in qib_7322_handle_hwerrors()
2165 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) | in qib_7322_handle_hwerrors()
2166 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) { in qib_7322_handle_hwerrors()
2175 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0))) in qib_7322_handle_hwerrors()
2178 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) in qib_7322_handle_hwerrors()
2293 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in qib_set_ib_7322_lstate()
2346 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); in set_vls()
2349 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); in set_vls()
2358 ~SYM_MASK(IBCCtrlA_0, NumVLane)) | in set_vls()
2387 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2393 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in qib_7322_bringup_serdes()
2443 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); in qib_7322_bringup_serdes()
2473 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); in qib_7322_bringup_serdes()
2491 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2500 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); in qib_7322_bringup_serdes()
2504 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); in qib_7322_bringup_serdes()
2548 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_mini_quiet_serdes()
2563 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); in qib_7322_mini_quiet_serdes()
2714 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2730 SYM_MASK(DCACtrlF, SendDma1DCAOPH) : in qib_update_sdma_dca()
2731 SYM_MASK(DCACtrlF, SendDma0DCAOPH)); in qib_update_sdma_dca()
2743 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) : in qib_update_sdma_dca()
2744 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable); in qib_update_sdma_dca()
2926 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2928 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
4001 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); in qib_7322_get_ib_cfg()
4029 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? in qib_7322_get_ib_cfg()
4150 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); in qib_7322_set_ib_cfg()
4164 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); in qib_7322_set_ib_cfg()
4184 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); in qib_7322_set_ib_cfg()
4187 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); in qib_7322_set_ib_cfg()
4201 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); in qib_7322_set_ib_cfg()
4330 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4336 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4387 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { in set_vl_weights()
4392 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); in set_vl_weights()
4496 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4498 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4500 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4502 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4504 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4506 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4519 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4637 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4639 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4641 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); in sendctrl_7322_mod()
4646 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4648 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4659 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4663 SYM_MASK(SendCtrl, Disarm) | i); in sendctrl_7322_mod()
4676 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | in sendctrl_7322_mod()
4677 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | in sendctrl_7322_mod()
4678 SYM_MASK(SendCtrl_0, TxeBypassIbc); in sendctrl_7322_mod()
4686 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | in sendctrl_7322_mod()
4690 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) in sendctrl_7322_mod()
4691 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
5193 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | in qib_7322_mini_pcs_reset()
5194 SYM_MASK(IBPCSConfig_0, xcv_treset) | in qib_7322_mini_pcs_reset()
5195 SYM_MASK(IBPCSConfig_0, tx_rx_reset); in qib_7322_mini_pcs_reset()
5202 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); in qib_7322_mini_pcs_reset()
5210 SYM_MASK(HwErrClear, statusValidNoEopClear)); in qib_7322_mini_pcs_reset()
5546 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { in qib_7322_ib_updown()
5549 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { in qib_7322_ib_updown()
5556 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { in qib_7322_ib_updown()
5570 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | in qib_7322_ib_updown()
5571 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); in qib_7322_ib_updown()
5582 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in qib_7322_ib_updown()
5833 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5834 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5835 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5836 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5837 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5838 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5839 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
6254 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); in write_7322_init_portregs()
6267 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); in write_7322_init_portregs()
6277 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); in write_7322_init_portregs()
6308 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); in write_7322_initregs()
6465 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | in qib_init_7322_variables()
6466 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | in qib_init_7322_variables()
6482 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6484 | SYM_MASK(HwErrMask, in qib_init_7322_variables()
6487 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | in qib_init_7322_variables()
6488 SYM_MASK(IntMask, SDmaIdleIntMask_0) | in qib_init_7322_variables()
6489 SYM_MASK(IntMask, SDmaProgressIntMask_0) | in qib_init_7322_variables()
6490 SYM_MASK(IntMask, SDmaIntMask_0) | in qib_init_7322_variables()
6491 SYM_MASK(IntMask, ErrIntMask_0) | in qib_init_7322_variables()
6492 SYM_MASK(IntMask, SendDoneIntMask_0)); in qib_init_7322_variables()
6497 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6499 | SYM_MASK(HwErrMask, in qib_init_7322_variables()
6502 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | in qib_init_7322_variables()
6503 SYM_MASK(IntMask, SDmaIdleIntMask_1) | in qib_init_7322_variables()
6504 SYM_MASK(IntMask, SDmaProgressIntMask_1) | in qib_init_7322_variables()
6505 SYM_MASK(IntMask, SDmaIntMask_1) | in qib_init_7322_variables()
6506 SYM_MASK(IntMask, ErrIntMask_1) | in qib_init_7322_variables()
6507 SYM_MASK(IntMask, SendDoneIntMask_1)); in qib_init_7322_variables()
6700 SYM_MASK(SendCtrl, SendBufAvailPad64Byte); in qib_init_7322_variables()
6966 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || in qib_sdma_7322_busy()
6967 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || in qib_sdma_7322_busy()
6968 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || in qib_sdma_7322_busy()
6969 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); in qib_sdma_7322_busy()
7119 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7139 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7731 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7734 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7836 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); in serdes_7322_los_enable()
7840 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); in serdes_7322_los_enable()
7868 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in serdes_7322_init_old()
7966 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in serdes_7322_init_new()
8195 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | in write_tx_serdes_param()
8196 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | in write_tx_serdes_param()
8197 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | in write_tx_serdes_param()
8198 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); in write_tx_serdes_param()
8200 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8251 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8478 SYM_MASK(Control, FreezeMode)); in check_7322_rxe_status()
8496 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); in check_7322_rxe_status()
8504 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); in check_7322_rxe_status()