1400 		if (vl == CNTR_INVALID_VL)  in dev_access_u32_csr()
1404 		if (vl != CNTR_INVALID_VL)  in dev_access_u32_csr()
1460 		if (vl == CNTR_INVALID_VL)  in dev_access_u64_csr()
1464 		if (vl != CNTR_INVALID_VL)  in dev_access_u64_csr()
1479 	if (vl != CNTR_INVALID_VL)  in dc_access_lcb_cntr()
1501 	if (vl != CNTR_INVALID_VL)  in port_access_u32_csr()
1514 		if (vl == CNTR_INVALID_VL)  in port_access_u64_csr()
1518 		if (vl != CNTR_INVALID_VL)  in port_access_u64_csr()
1551 	if (vl != CNTR_INVALID_VL)  in access_sw_link_dn_cnt()
1561 	if (vl != CNTR_INVALID_VL)  in access_sw_link_up_cnt()
1572 	if (vl != CNTR_INVALID_VL)  in access_sw_unknown_frame_cnt()
1584 	if (vl == CNTR_INVALID_VL)  in access_sw_xmit_discards()
1600 	if (vl != CNTR_INVALID_VL)  in access_xmit_constraint_errs()
1612 	if (vl != CNTR_INVALID_VL)  in access_rcv_constraint_errs()
1635 	if (vl != CNTR_INVALID_VL)  in read_write_cpu()
4085 	if (vl != CNTR_INVALID_VL)					      \
5546 	u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);  in update_rcverr_timer()
12070 							CNTR_INVALID_VL,  in hfi1_read_cntrs()
12122 						       CNTR_INVALID_VL,  in hfi1_read_portcntrs()
12260 	if (vl != CNTR_INVALID_VL)  in read_dev_cntr()
12274 	if (vl != CNTR_INVALID_VL)  in write_dev_cntr()
12288 	if (vl != CNTR_INVALID_VL)  in read_port_cntr()
12308 	if (vl != CNTR_INVALID_VL)  in write_port_cntr()
12339 	cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);  in do_update_synth_timer()
12342 	cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);  in do_update_synth_timer()
12377 				read_dev_cntr(dd, i, CNTR_INVALID_VL);  in do_update_synth_timer()
12388 					read_port_cntr(ppd, j, CNTR_INVALID_VL);  in do_update_synth_timer()
12400 		dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,  in do_update_synth_timer()
12404 		dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,  in do_update_synth_timer()