106 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,  in xadc_write_reg()  argument
109 	writel(val, xadc->base + reg);  in xadc_write_reg()
112 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,  in xadc_read_reg()  argument
115 	*val = readl(xadc->base + reg);  in xadc_read_reg()
128 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,  in xadc_zynq_write_fifo()  argument
134 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);  in xadc_zynq_write_fifo()
137 static void xadc_zynq_drain_fifo(struct xadc *xadc)  in xadc_zynq_drain_fifo()  argument
141 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
144 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_drain_fifo()
145 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
149 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,  in xadc_zynq_update_intmsk()  argument
152 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
153 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
155 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,  in xadc_zynq_update_intmsk()
156 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
159 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_write_adc_reg()  argument
166 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
167 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_write_adc_reg()
170 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
173 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_write_adc_reg()
174 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_write_adc_reg()
177 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_write_adc_reg()
179 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_write_adc_reg()
180 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
182 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
188 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_write_adc_reg()
193 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_read_adc_reg()  argument
203 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
204 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_read_adc_reg()
206 	xadc_zynq_drain_fifo(xadc);  in xadc_zynq_read_adc_reg()
207 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
209 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_read_adc_reg()
210 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_read_adc_reg()
213 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_read_adc_reg()
215 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_read_adc_reg()
216 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
217 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
223 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
224 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
248 	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);  in xadc_zynq_unmask_worker()  local
251 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);  in xadc_zynq_unmask_worker()
255 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
258 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
259 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
262 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
265 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);  in xadc_zynq_unmask_worker()
267 	xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_unmask_worker()
269 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
272 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
273 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
282 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_interrupt_handler()  local
285 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_interrupt_handler()
287 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
292 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
294 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);  in xadc_zynq_interrupt_handler()
297 		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_interrupt_handler()
299 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
304 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
309 		xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_interrupt_handler()
315 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
318 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
330 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_setup()  local
342 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
344 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
349 		ret = clk_set_rate(xadc->clk,  in xadc_zynq_setup()
372 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);  in xadc_zynq_setup()
373 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);  in xadc_zynq_setup()
374 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);  in xadc_zynq_setup()
375 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
376 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |  in xadc_zynq_setup()
381 		ret = clk_set_rate(xadc->clk, pcap_rate);  in xadc_zynq_setup()
389 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)  in xadc_zynq_get_dclk_rate()  argument
394 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);  in xadc_zynq_get_dclk_rate()
411 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
414 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_zynq_update_alarm()  argument
422 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
425 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_update_alarm()
426 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);  in xadc_zynq_update_alarm()
428 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,  in xadc_zynq_update_alarm()
431 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
443 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_read_adc_reg()  argument
448 	xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);  in xadc_axi_read_adc_reg()
454 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_write_adc_reg()  argument
457 	xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);  in xadc_axi_write_adc_reg()
465 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_setup()  local
467 	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);  in xadc_axi_setup()
468 	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);  in xadc_axi_setup()
476 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_interrupt_handler()  local
480 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);  in xadc_axi_interrupt_handler()
481 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);  in xadc_axi_interrupt_handler()
487 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
488 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
503 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);  in xadc_axi_interrupt_handler()
508 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_axi_update_alarm()  argument
522 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
523 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_axi_update_alarm()
526 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_axi_update_alarm()
527 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
530 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)  in xadc_axi_get_dclk()  argument
532 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
545 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in _xadc_update_adc_reg()  argument
551 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);  in _xadc_update_adc_reg()
555 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);  in _xadc_update_adc_reg()
558 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_update_adc_reg()  argument
563 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
564 	ret = _xadc_update_adc_reg(xadc, reg, mask, val);  in xadc_update_adc_reg()
565 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
570 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)  in xadc_get_dclk_rate()  argument
572 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
578 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_update_scan_mode()  local
583 	kfree(xadc->data);  in xadc_update_scan_mode()
584 	xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);  in xadc_update_scan_mode()
585 	if (!xadc->data)  in xadc_update_scan_mode()
623 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_trigger_handler()  local
627 	if (!xadc->data)  in xadc_trigger_handler()
634 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
638 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
648 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);  in xadc_trigger_set_state()  local
654 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
658 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
662 			xadc->trigger = trigger;  in xadc_trigger_set_state()
663 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
668 		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,  in xadc_trigger_set_state()
673 		xadc->trigger = NULL;  in xadc_trigger_set_state()
676 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
677 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_trigger_set_state()
678 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS);  in xadc_trigger_set_state()
683 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_trigger_set_state()
684 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
687 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
722 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)  in xadc_power_adc_b()  argument
736 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,  in xadc_power_adc_b()
740 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)  in xadc_get_seq_mode()  argument
744 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
756 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_postdisable()  local
766 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_postdisable()
770 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_postdisable()
774 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_postdisable()
779 	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);  in xadc_postdisable()
784 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_preenable()  local
789 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
795 	seq_mode = xadc_get_seq_mode(xadc, scan_mask);  in xadc_preenable()
797 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_preenable()
801 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_preenable()
805 	ret = xadc_power_adc_b(xadc, seq_mode);  in xadc_preenable()
809 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
830 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_read_raw()  local
839 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
884 		ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);  in xadc_read_raw()
892 		*val = xadc_get_dclk_rate(xadc) / div / 26;  in xadc_read_raw()
903 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_write_raw()  local
904 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);  in xadc_write_raw()
938 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,  in xadc_write_raw()
1060 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_parse_dt()  local
1073 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1075 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1077 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1081 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1087 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1156 	struct xadc *xadc;  in xadc_probe()  local
1172 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));  in xadc_probe()
1176 	xadc = iio_priv(indio_dev);  in xadc_probe()
1177 	xadc->ops = id->data;  in xadc_probe()
1178 	xadc->irq = irq;  in xadc_probe()
1179 	init_completion(&xadc->completion);  in xadc_probe()
1180 	mutex_init(&xadc->mutex);  in xadc_probe()
1181 	spin_lock_init(&xadc->lock);  in xadc_probe()
1182 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1185 	xadc->base = devm_ioremap_resource(&pdev->dev, mem);  in xadc_probe()
1186 	if (IS_ERR(xadc->base))  in xadc_probe()
1187 		return PTR_ERR(xadc->base);  in xadc_probe()
1199 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1206 		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1207 		if (IS_ERR(xadc->convst_trigger)) {  in xadc_probe()
1208 			ret = PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1211 		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1213 		if (IS_ERR(xadc->samplerate_trigger)) {  in xadc_probe()
1214 			ret = PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1219 	xadc->clk = devm_clk_get(&pdev->dev, NULL);  in xadc_probe()
1220 	if (IS_ERR(xadc->clk)) {  in xadc_probe()
1221 		ret = PTR_ERR(xadc->clk);  in xadc_probe()
1225 	ret = clk_prepare_enable(xadc->clk);  in xadc_probe()
1229 	ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0,  in xadc_probe()
1234 	ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);  in xadc_probe()
1239 		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1240 			&xadc->threshold[i]);  in xadc_probe()
1242 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);  in xadc_probe()
1252 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);  in xadc_probe()
1255 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),  in xadc_probe()
1261 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,  in xadc_probe()
1273 			xadc->threshold[i] = 0xffff;  in xadc_probe()
1275 			xadc->threshold[i] = 0;  in xadc_probe()
1276 		xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1277 			xadc->threshold[i]);  in xadc_probe()
1292 	free_irq(xadc->irq, indio_dev);  in xadc_probe()
1294 	clk_disable_unprepare(xadc->clk);  in xadc_probe()
1296 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1297 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_probe()
1299 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1300 		iio_trigger_free(xadc->convst_trigger);  in xadc_probe()
1302 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1313 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_remove()  local
1316 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_remove()
1317 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_remove()
1318 		iio_trigger_free(xadc->convst_trigger);  in xadc_remove()
1321 	free_irq(xadc->irq, indio_dev);  in xadc_remove()
1322 	clk_disable_unprepare(xadc->clk);  in xadc_remove()
1323 	cancel_delayed_work(&xadc->zynq_unmask_work);  in xadc_remove()
1324 	kfree(xadc->data);  in xadc_remove()