Lines Matching refs:STM32F7_I2C_CR1
36 #define STM32F7_I2C_CR1 0x00 macro
366 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
615 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_dma_req()
644 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
647 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
649 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
728 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
775 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
843 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
861 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_xfer_msg()
1006 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_xfer_msg()
1020 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_rep_start()
1090 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_smbus_rep_start()
1174 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1179 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1197 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_slave_start()
1724 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_reg_slave()