320 #define idma_mask(ch)			(1 << ((ch) & 0x1f))  macro
338 	ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));  in __ipu_idmac_reset_current_buffer()
352 		reg |= idma_mask(channel->num);  in ipu_idmac_set_double_buffer()
354 		reg &= ~idma_mask(channel->num);  in ipu_idmac_set_double_buffer()
497 	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;  in ipu_idmac_get_current_buffer()
521 	return ((reg & idma_mask(channel->num)) != 0);  in ipu_idmac_buffer_is_ready()
535 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));  in ipu_idmac_select_buffer()
537 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));  in ipu_idmac_select_buffer()
554 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));  in ipu_idmac_clear_buffer()
557 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));  in ipu_idmac_clear_buffer()
560 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));  in ipu_idmac_clear_buffer()
580 	val |= idma_mask(channel->num);  in ipu_idmac_enable_channel()
591 	return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));  in ipu_idmac_channel_busy()
602 			idma_mask(channel->num)) {  in ipu_idmac_wait_busy()
622 	val &= ~idma_mask(channel->num);  in ipu_idmac_disable_channel()
631 			idma_mask(channel->num)) {  in ipu_idmac_disable_channel()
632 		ipu_cm_write(ipu, idma_mask(channel->num),  in ipu_idmac_disable_channel()
637 			idma_mask(channel->num)) {  in ipu_idmac_disable_channel()
638 		ipu_cm_write(ipu, idma_mask(channel->num),  in ipu_idmac_disable_channel()
646 	val &= ~idma_mask(channel->num);  in ipu_idmac_disable_channel()