230 	zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);  in vou_inf_hdmi_audio_sel()
245 		zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,  in vou_inf_enable()
247 		zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,  in vou_inf_enable()
251 		zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,  in vou_inf_enable()
254 		zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);  in vou_inf_enable()
255 		zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);  in vou_inf_enable()
259 	zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,  in vou_inf_enable()
263 	zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,  in vou_inf_enable()
267 	zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,  in vou_inf_enable()
271 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,  in vou_inf_enable()
275 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);  in vou_inf_enable()
284 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);  in vou_inf_disable()
287 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);  in vou_inf_disable()
299 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);  in zx_vou_config_dividers()
339 		zx_writel_mask(vou->vouctl + reg, 0x7 << shift,  in zx_vou_config_dividers()
344 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,  in zx_vou_config_dividers()
410 	zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,  in zx_crtc_atomic_enable()
422 	zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask,  in zx_crtc_atomic_enable()
426 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,  in zx_crtc_atomic_enable()
430 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,  in zx_crtc_atomic_enable()
432 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,  in zx_crtc_atomic_enable()
436 	zx_writel_mask(zcrtc->chnreg + CHN_INTERLACE_BUF_CTRL, CHN_INTERLACE_EN,  in zx_crtc_atomic_enable()
443 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);  in zx_crtc_atomic_enable()
470 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);  in zx_crtc_atomic_disable()
473 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);  in zx_crtc_atomic_disable()
506 	zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,  in zx_vou_enable_vblank()
517 	zx_writel_mask(vou->timing + TIMING_INT_CTRL,  in zx_vou_disable_vblank()
618 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);  in zx_vou_layer_enable()
619 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);  in zx_vou_layer_enable()
621 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,  in zx_vou_layer_enable()
623 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,  in zx_vou_layer_enable()
627 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);  in zx_vou_layer_enable()
638 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);  in zx_vou_layer_disable()
717 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,  in vou_dtrc_init()
721 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,  in vou_dtrc_init()
725 	zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,  in vou_dtrc_init()
727 	zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,  in vou_dtrc_init()
758 	zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);  in vou_hw_init()