182 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))  macro
281 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);  in vc4_vec_ntsc_mode_set()
282 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_ntsc_mode_set()
287 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);  in vc4_vec_ntsc_j_mode_set()
288 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_ntsc_j_mode_set()
300 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);  in vc4_vec_pal_mode_set()
301 	VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);  in vc4_vec_pal_mode_set()
306 	VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);  in vc4_vec_pal_m_mode_set()
307 	VEC_WRITE(VEC_CONFIG1,  in vc4_vec_pal_m_mode_set()
309 	VEC_WRITE(VEC_FREQ3_2, 0x223b);  in vc4_vec_pal_m_mode_set()
310 	VEC_WRITE(VEC_FREQ1_0, 0x61d1);  in vc4_vec_pal_m_mode_set()
422 	VEC_WRITE(VEC_CFG, 0);  in vc4_vec_encoder_disable()
423 	VEC_WRITE(VEC_DAC_MISC,  in vc4_vec_encoder_disable()
470 	VEC_WRITE(VEC_WSE_RESET, 1);  in vc4_vec_encoder_enable()
471 	VEC_WRITE(VEC_SOFT_RESET, 1);  in vc4_vec_encoder_enable()
474 	VEC_WRITE(VEC_WSE_CONTROL, 0);  in vc4_vec_encoder_enable()
482 	VEC_WRITE(VEC_SCHPH, 0x28);  in vc4_vec_encoder_enable()
487 	VEC_WRITE(VEC_CLMP0_START, 0xac);  in vc4_vec_encoder_enable()
488 	VEC_WRITE(VEC_CLMP0_END, 0xec);  in vc4_vec_encoder_enable()
489 	VEC_WRITE(VEC_CONFIG2,  in vc4_vec_encoder_enable()
491 	VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);  in vc4_vec_encoder_enable()
492 	VEC_WRITE(VEC_DAC_CONFIG,  in vc4_vec_encoder_enable()
498 	VEC_WRITE(VEC_MASK0, 0);  in vc4_vec_encoder_enable()
502 	VEC_WRITE(VEC_DAC_MISC,  in vc4_vec_encoder_enable()
504 	VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);  in vc4_vec_encoder_enable()