103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)  macro
353 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,  in vc4_hdmi_stop_packet()
386 		HDMI_WRITE(packet_reg,  in vc4_hdmi_write_infoframe()
392 		HDMI_WRITE(packet_reg,  in vc4_hdmi_write_infoframe()
400 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,  in vc4_hdmi_write_infoframe()
479 	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);  in vc4_hdmi_encoder_disable()
481 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_encoder_disable()
540 	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,  in vc4_hdmi_encoder_enable()
544 	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);  in vc4_hdmi_encoder_enable()
549 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_encoder_enable()
551 	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);  in vc4_hdmi_encoder_enable()
560 	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,  in vc4_hdmi_encoder_enable()
565 	HDMI_WRITE(VC4_HDMI_HORZA,  in vc4_hdmi_encoder_enable()
571 	HDMI_WRITE(VC4_HDMI_HORZB,  in vc4_hdmi_encoder_enable()
582 	HDMI_WRITE(VC4_HDMI_VERTA0, verta);  in vc4_hdmi_encoder_enable()
583 	HDMI_WRITE(VC4_HDMI_VERTA1, verta);  in vc4_hdmi_encoder_enable()
585 	HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);  in vc4_hdmi_encoder_enable()
586 	HDMI_WRITE(VC4_HDMI_VERTB1, vertb);  in vc4_hdmi_encoder_enable()
627 	HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);  in vc4_hdmi_encoder_enable()
641 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,  in vc4_hdmi_encoder_enable()
650 		HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,  in vc4_hdmi_encoder_enable()
653 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,  in vc4_hdmi_encoder_enable()
668 		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,  in vc4_hdmi_encoder_enable()
672 		HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,  in vc4_hdmi_encoder_enable()
680 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,  in vc4_hdmi_encoder_enable()
682 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,  in vc4_hdmi_encoder_enable()
685 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,  in vc4_hdmi_encoder_enable()
687 		HDMI_WRITE(VC4_HDMI_FIFO_CTL,  in vc4_hdmi_encoder_enable()
753 	HDMI_WRITE(VC4_HDMI_CRP_CFG,  in vc4_hdmi_set_n_cts()
762 	HDMI_WRITE(VC4_HDMI_CTS_0, cts);  in vc4_hdmi_set_n_cts()
763 	HDMI_WRITE(VC4_HDMI_CTS_1, cts);  in vc4_hdmi_set_n_cts()
895 	HDMI_WRITE(VC4_HDMI_MAI_CONFIG,  in vc4_hdmi_audio_hw_params()
905 	HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);  in vc4_hdmi_audio_hw_params()
906 	HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);  in vc4_hdmi_audio_hw_params()
923 		HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,  in vc4_hdmi_audio_trigger()
936 		HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,  in vc4_hdmi_audio_trigger()
1198 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);  in vc4_cec_irq_handler()
1204 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);  in vc4_cec_irq_handler()
1205 	HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);  in vc4_cec_irq_handler()
1224 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |  in vc4_hdmi_cec_adap_enable()
1226 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);  in vc4_hdmi_cec_adap_enable()
1227 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,  in vc4_hdmi_cec_adap_enable()
1233 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,  in vc4_hdmi_cec_adap_enable()
1238 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,  in vc4_hdmi_cec_adap_enable()
1244 		HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);  in vc4_hdmi_cec_adap_enable()
1246 		HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);  in vc4_hdmi_cec_adap_enable()
1247 		HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |  in vc4_hdmi_cec_adap_enable()
1257 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,  in vc4_hdmi_cec_adap_log_addr()
1271 		HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,  in vc4_hdmi_cec_adap_transmit()
1279 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);  in vc4_hdmi_cec_adap_transmit()
1284 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);  in vc4_hdmi_cec_adap_transmit()
1415 	HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);  in vc4_hdmi_bind()
1425 	HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);  in vc4_hdmi_bind()