Lines Matching refs:HDMI_REG
138 #define HDMI_REG(reg) { reg, #reg } macro
143 HDMI_REG(VC4_HDMI_CORE_REV),
144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
145 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
146 HDMI_REG(VC4_HDMI_HOTPLUG),
147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
148 HDMI_REG(VC4_HDMI_MAI_CONFIG),
149 HDMI_REG(VC4_HDMI_MAI_FORMAT),
150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
152 HDMI_REG(VC4_HDMI_HORZA),
153 HDMI_REG(VC4_HDMI_HORZB),
154 HDMI_REG(VC4_HDMI_FIFO_CTL),
155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
156 HDMI_REG(VC4_HDMI_VERTA0),
157 HDMI_REG(VC4_HDMI_VERTA1),
158 HDMI_REG(VC4_HDMI_VERTB0),
159 HDMI_REG(VC4_HDMI_VERTB1),
160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
168 HDMI_REG(VC4_HDMI_CPU_STATUS),
169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
185 HDMI_REG(VC4_HD_M_CTL),
186 HDMI_REG(VC4_HD_MAI_CTL),
187 HDMI_REG(VC4_HD_MAI_THR),
188 HDMI_REG(VC4_HD_MAI_FMT),
189 HDMI_REG(VC4_HD_MAI_SMP),
190 HDMI_REG(VC4_HD_VID_CTL),
191 HDMI_REG(VC4_HD_CSC_CTL),
192 HDMI_REG(VC4_HD_FRAME_COUNT),