592 #define DSI_PORT_WRITE(offset, val) \  macro
733 	DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_latch_ulps()
762 	DSI_PORT_WRITE(STAT, stat_ulps);  in vc4_dsi_ulps()
763 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);  in vc4_dsi_ulps()
769 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
781 	DSI_PORT_WRITE(STAT, stat_stop);  in vc4_dsi_ulps()
782 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
788 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
919 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_encoder_enable()
923 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_encoder_enable()
928 	DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));  in vc4_dsi_encoder_enable()
941 		DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_encoder_enable()
943 		DSI_PORT_WRITE(PHY_AFEC1,  in vc4_dsi_encoder_enable()
965 		DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_encoder_enable()
967 		DSI_PORT_WRITE(PHY_AFEC1, 0);  in vc4_dsi_encoder_enable()
1012 	DSI_PORT_WRITE(HS_CLT0,  in vc4_dsi_encoder_enable()
1020 	DSI_PORT_WRITE(HS_CLT1,  in vc4_dsi_encoder_enable()
1026 	DSI_PORT_WRITE(HS_CLT2,  in vc4_dsi_encoder_enable()
1030 	DSI_PORT_WRITE(HS_DLT3,  in vc4_dsi_encoder_enable()
1038 	DSI_PORT_WRITE(HS_DLT4,  in vc4_dsi_encoder_enable()
1055 	DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,  in vc4_dsi_encoder_enable()
1059 	DSI_PORT_WRITE(HS_DLT6,  in vc4_dsi_encoder_enable()
1065 	DSI_PORT_WRITE(HS_DLT7,  in vc4_dsi_encoder_enable()
1069 	DSI_PORT_WRITE(PHYC,  in vc4_dsi_encoder_enable()
1081 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_encoder_enable()
1086 	DSI_PORT_WRITE(HSTX_TO_CNT, 0);  in vc4_dsi_encoder_enable()
1088 	DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);  in vc4_dsi_encoder_enable()
1090 	DSI_PORT_WRITE(TA_TO_CNT, 100000);  in vc4_dsi_encoder_enable()
1092 	DSI_PORT_WRITE(PR_TO_CNT, 100000);  in vc4_dsi_encoder_enable()
1097 	DSI_PORT_WRITE(DISP1_CTRL,  in vc4_dsi_encoder_enable()
1104 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);  in vc4_dsi_encoder_enable()
1106 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);  in vc4_dsi_encoder_enable()
1111 		DSI_PORT_WRITE(PHY_AFEC0,  in vc4_dsi_encoder_enable()
1121 		DSI_PORT_WRITE(DISP0_CTRL,  in vc4_dsi_encoder_enable()
1130 		DSI_PORT_WRITE(DISP0_CTRL,  in vc4_dsi_encoder_enable()
1193 		DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);  in vc4_dsi_host_transfer()
1197 		DSI_PORT_WRITE(TXPKT_PIX_FIFO,  in vc4_dsi_host_transfer()
1226 	DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);  in vc4_dsi_host_transfer()
1228 		DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |  in vc4_dsi_host_transfer()
1231 		DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |  in vc4_dsi_host_transfer()
1236 	DSI_PORT_WRITE(TXPKT1H, pkth);  in vc4_dsi_host_transfer()
1237 	DSI_PORT_WRITE(TXPKT1C, pktc);  in vc4_dsi_host_transfer()
1249 	DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);  in vc4_dsi_host_transfer()
1288 	DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);  in vc4_dsi_host_transfer()
1290 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_host_transfer()
1294 	DSI_PORT_WRITE(TXPKT1C, 0);  in vc4_dsi_host_transfer()
1295 	DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);  in vc4_dsi_host_transfer()
1401 	DSI_PORT_WRITE(INT_STAT, stat);  in vc4_dsi_irq_handler()
1570 	DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);  in vc4_dsi_bind()
1572 	DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));  in vc4_dsi_bind()