Lines Matching refs:v3d
107 struct v3d_dev *v3d; member
162 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
163 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
165 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
166 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
168 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
169 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
171 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
172 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
192 struct v3d_dev *v3d; member
272 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
282 void v3d_reset(struct v3d_dev *v3d);
283 void v3d_invalidate_caches(struct v3d_dev *v3d);
284 void v3d_flush_caches(struct v3d_dev *v3d);
287 void v3d_irq_init(struct v3d_dev *v3d);
288 void v3d_irq_enable(struct v3d_dev *v3d);
289 void v3d_irq_disable(struct v3d_dev *v3d);
290 void v3d_irq_reset(struct v3d_dev *v3d);
295 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
300 int v3d_sched_init(struct v3d_dev *v3d);
301 void v3d_sched_fini(struct v3d_dev *v3d);