Lines Matching refs:tx_pu_value
50 u8 tx_pu_value; member
70 .tx_pu_value = 0x10,
85 .tx_pu_value = 0x40,
100 .tx_pu_value = 0x66,
115 .tx_pu_value = 0x66,
130 .tx_pu_value = 0x66,
149 .tx_pu_value = 0x40,
164 .tx_pu_value = 0x66,
179 .tx_pu_value = 0x66,
194 .tx_pu_value = 0x66,
214 .tx_pu_value = 0,
229 .tx_pu_value = 0,
244 .tx_pu_value = 0x66 /* 0 */,
259 .tx_pu_value = 64,
274 .tx_pu_value = 96,
2468 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()