Lines Matching refs:tegra_sor_writel
406 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() function
463 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
536 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
542 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
548 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
551 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_train_fast()
557 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
562 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
569 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
582 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
594 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
603 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
618 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
631 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
632 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
633 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
638 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
639 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
640 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
650 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
657 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
680 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
686 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
728 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
926 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
945 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
950 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
955 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1012 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1020 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1027 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1034 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1041 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1044 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1054 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1071 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1077 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1104 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1129 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1134 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1151 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1157 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1162 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1204 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1208 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1212 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1218 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1525 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_edp_disable()
1648 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1670 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_edp_enable()
1683 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1693 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1699 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1719 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1745 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_edp_enable()
1746 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_edp_enable()
1771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1781 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1795 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1803 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1812 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1817 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1837 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1846 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1857 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1872 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1878 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
2003 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
2015 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2020 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2038 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2058 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2069 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2091 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2119 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2173 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2236 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2242 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2247 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2251 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2258 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2265 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2277 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2300 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2315 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2319 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2323 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2324 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2337 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2338 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2377 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2409 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2414 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2431 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2451 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2457 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2463 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2469 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2474 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2530 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2536 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()