Lines Matching refs:SOR_DP_LINKCTL0
923 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
926 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1307 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1773 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1800 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1803 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1846 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
2305 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()