116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,  in tegra_dsi_writel()  function
376 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);  in tegra_dsi_set_phy_timing()
382 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);  in tegra_dsi_set_phy_timing()
387 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);  in tegra_dsi_set_phy_timing()
392 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);  in tegra_dsi_set_phy_timing()
457 	tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);  in tegra_dsi_ganged_enable()
458 	tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);  in tegra_dsi_ganged_enable()
461 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_enable()
470 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_enable()
519 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
521 	tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);  in tegra_dsi_configure()
524 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_configure()
541 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_configure()
544 		tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);  in tegra_dsi_configure()
567 		tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);  in tegra_dsi_configure()
568 		tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);  in tegra_dsi_configure()
569 		tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);  in tegra_dsi_configure()
570 		tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);  in tegra_dsi_configure()
573 		tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);  in tegra_dsi_configure()
589 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);  in tegra_dsi_configure()
590 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);  in tegra_dsi_configure()
591 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);  in tegra_dsi_configure()
592 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);  in tegra_dsi_configure()
596 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);  in tegra_dsi_configure()
617 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);  in tegra_dsi_configure()
656 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_video_disable()
664 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);  in tegra_dsi_ganged_disable()
665 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);  in tegra_dsi_ganged_disable()
666 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);  in tegra_dsi_ganged_disable()
674 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_enable()
687 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);  in tegra_dsi_pad_calibrate()
688 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);  in tegra_dsi_pad_calibrate()
689 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
690 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);  in tegra_dsi_pad_calibrate()
691 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);  in tegra_dsi_pad_calibrate()
699 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);  in tegra_dsi_pad_calibrate()
703 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);  in tegra_dsi_pad_calibrate()
717 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);  in tegra_dsi_set_timeout()
722 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);  in tegra_dsi_set_timeout()
725 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);  in tegra_dsi_set_timeout()
742 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_disable()
756 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
762 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_soft_reset()
768 		tegra_dsi_writel(dsi, 0, DSI_TRIGGER);  in tegra_dsi_soft_reset()
1186 	tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);  in tegra_dsi_transmit()
1234 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_writesl()
1262 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1268 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);  in tegra_dsi_host_transfer()
1285 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1295 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);  in tegra_dsi_host_transfer()
1299 	tegra_dsi_writel(dsi, value, DSI_CONTROL);  in tegra_dsi_host_transfer()
1303 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);  in tegra_dsi_host_transfer()