Lines Matching refs:phy
18 struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_config_a83t() argument
21 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_hdmi_phy_config_a83t()
80 struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_config_h3() argument
148 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_hdmi_phy_config_h3()
158 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_hdmi_phy_config_h3()
183 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_config_h3()
190 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
193 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, in sun8i_hdmi_phy_config_h3()
197 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG, in sun8i_hdmi_phy_config_h3()
199 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
205 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_hdmi_phy_config_h3()
210 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
215 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_config_h3()
219 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end); in sun8i_hdmi_phy_config_h3()
220 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init); in sun8i_hdmi_phy_config_h3()
221 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init); in sun8i_hdmi_phy_config_h3()
229 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; in sun8i_hdmi_phy_config() local
238 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_config()
241 if (phy->variant->has_phy_clk) in sun8i_hdmi_phy_config()
242 clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000); in sun8i_hdmi_phy_config()
244 return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000); in sun8i_hdmi_phy_config()
248 struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_disable_a83t() argument
253 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_hdmi_phy_disable_a83t()
258 struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_disable_h3() argument
260 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_disable_h3()
264 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0); in sun8i_hdmi_phy_disable_h3()
269 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; in sun8i_hdmi_phy_disable() local
271 phy->variant->phy_disable(hdmi, phy); in sun8i_hdmi_phy_disable()
282 static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_a83t() argument
284 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
292 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
297 static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_h3() argument
301 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0); in sun8i_hdmi_phy_init_h3()
302 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
306 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
309 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
313 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
317 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
321 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
325 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
328 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
337 regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val, in sun8i_hdmi_phy_init_h3()
341 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
344 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
355 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, in sun8i_hdmi_phy_init_h3()
362 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_init_h3()
366 regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); in sun8i_hdmi_phy_init_h3()
369 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_hdmi_phy_init_h3()
370 phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; in sun8i_hdmi_phy_init_h3()
373 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init() argument
376 regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG, in sun8i_hdmi_phy_init()
380 regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG, in sun8i_hdmi_phy_init()
383 phy->variant->phy_init(phy); in sun8i_hdmi_phy_init()
439 struct sun8i_hdmi_phy *phy; in sun8i_hdmi_phy_probe() local
450 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in sun8i_hdmi_phy_probe()
451 if (!phy) in sun8i_hdmi_phy_probe()
454 phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; in sun8i_hdmi_phy_probe()
468 phy->regs = devm_regmap_init_mmio(dev, regs, in sun8i_hdmi_phy_probe()
470 if (IS_ERR(phy->regs)) { in sun8i_hdmi_phy_probe()
472 return PTR_ERR(phy->regs); in sun8i_hdmi_phy_probe()
475 phy->clk_bus = of_clk_get_by_name(node, "bus"); in sun8i_hdmi_phy_probe()
476 if (IS_ERR(phy->clk_bus)) { in sun8i_hdmi_phy_probe()
478 return PTR_ERR(phy->clk_bus); in sun8i_hdmi_phy_probe()
481 phy->clk_mod = of_clk_get_by_name(node, "mod"); in sun8i_hdmi_phy_probe()
482 if (IS_ERR(phy->clk_mod)) { in sun8i_hdmi_phy_probe()
484 ret = PTR_ERR(phy->clk_mod); in sun8i_hdmi_phy_probe()
488 if (phy->variant->has_phy_clk) { in sun8i_hdmi_phy_probe()
489 phy->clk_pll0 = of_clk_get_by_name(node, "pll-0"); in sun8i_hdmi_phy_probe()
490 if (IS_ERR(phy->clk_pll0)) { in sun8i_hdmi_phy_probe()
492 ret = PTR_ERR(phy->clk_pll0); in sun8i_hdmi_phy_probe()
496 if (phy->variant->has_second_pll) { in sun8i_hdmi_phy_probe()
497 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); in sun8i_hdmi_phy_probe()
498 if (IS_ERR(phy->clk_pll1)) { in sun8i_hdmi_phy_probe()
500 ret = PTR_ERR(phy->clk_pll1); in sun8i_hdmi_phy_probe()
505 ret = sun8i_phy_clk_create(phy, dev, in sun8i_hdmi_phy_probe()
506 phy->variant->has_second_pll); in sun8i_hdmi_phy_probe()
512 clk_prepare_enable(phy->clk_phy); in sun8i_hdmi_phy_probe()
515 phy->rst_phy = of_reset_control_get_shared(node, "phy"); in sun8i_hdmi_phy_probe()
516 if (IS_ERR(phy->rst_phy)) { in sun8i_hdmi_phy_probe()
518 ret = PTR_ERR(phy->rst_phy); in sun8i_hdmi_phy_probe()
522 ret = reset_control_deassert(phy->rst_phy); in sun8i_hdmi_phy_probe()
528 ret = clk_prepare_enable(phy->clk_bus); in sun8i_hdmi_phy_probe()
534 ret = clk_prepare_enable(phy->clk_mod); in sun8i_hdmi_phy_probe()
540 hdmi->phy = phy; in sun8i_hdmi_phy_probe()
545 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_probe()
547 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_probe()
549 reset_control_put(phy->rst_phy); in sun8i_hdmi_phy_probe()
551 clk_disable_unprepare(phy->clk_phy); in sun8i_hdmi_phy_probe()
553 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_probe()
555 clk_put(phy->clk_pll0); in sun8i_hdmi_phy_probe()
557 clk_put(phy->clk_mod); in sun8i_hdmi_phy_probe()
559 clk_put(phy->clk_bus); in sun8i_hdmi_phy_probe()
566 struct sun8i_hdmi_phy *phy = hdmi->phy; in sun8i_hdmi_phy_remove() local
568 clk_disable_unprepare(phy->clk_mod); in sun8i_hdmi_phy_remove()
569 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_remove()
570 clk_disable_unprepare(phy->clk_phy); in sun8i_hdmi_phy_remove()
572 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_remove()
574 reset_control_put(phy->rst_phy); in sun8i_hdmi_phy_remove()
576 clk_put(phy->clk_pll0); in sun8i_hdmi_phy_remove()
577 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_remove()
578 clk_put(phy->clk_mod); in sun8i_hdmi_phy_remove()
579 clk_put(phy->clk_bus); in sun8i_hdmi_phy_remove()