81 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,  in sun4i_tcon_channel_set_status()  argument
88 		WARN_ON(!tcon->quirks->has_channel_0);  in sun4i_tcon_channel_set_status()
89 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,  in sun4i_tcon_channel_set_status()
92 		clk = tcon->dclk;  in sun4i_tcon_channel_set_status()
95 		WARN_ON(!tcon->quirks->has_channel_1);  in sun4i_tcon_channel_set_status()
96 		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,  in sun4i_tcon_channel_set_status()
99 		clk = tcon->sclk1;  in sun4i_tcon_channel_set_status()
115 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,  in sun4i_tcon_lvds_set_status()  argument
122 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,  in sun4i_tcon_lvds_set_status()
131 		regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,  in sun4i_tcon_lvds_set_status()
138 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,  in sun4i_tcon_lvds_set_status()
143 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,  in sun4i_tcon_lvds_set_status()
152 		regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,  in sun4i_tcon_lvds_set_status()
156 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,  in sun4i_tcon_lvds_set_status()
161 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,  in sun4i_tcon_set_status()  argument
186 		sun4i_tcon_lvds_set_status(tcon, encoder, false);  in sun4i_tcon_set_status()
188 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,  in sun4i_tcon_set_status()
193 		sun4i_tcon_lvds_set_status(tcon, encoder, true);  in sun4i_tcon_set_status()
195 	sun4i_tcon_channel_set_status(tcon, channel, enabled);  in sun4i_tcon_set_status()
198 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)  in sun4i_tcon_enable_vblank()  argument
211 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);  in sun4i_tcon_enable_vblank()
224 	struct sun4i_tcon *tcon;  in sun4i_get_tcon0()  local
226 	list_for_each_entry(tcon, &drv->tcon_list, list)  in sun4i_get_tcon0()
227 		if (tcon->id == 0)  in sun4i_get_tcon0()
228 			return tcon;  in sun4i_get_tcon0()
236 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,  in sun4i_tcon_set_mux()  argument
241 	if (tcon->quirks->set_mux)  in sun4i_tcon_set_mux()
242 		ret = tcon->quirks->set_mux(tcon, encoder);  in sun4i_tcon_set_mux()
266 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,  in sun4i_tcon0_mode_set_common()  argument
270 	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);  in sun4i_tcon0_mode_set_common()
273 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,  in sun4i_tcon0_mode_set_common()
278 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,  in sun4i_tcon0_mode_set_cpu()  argument
287 	tcon->dclk_min_div = 4;  in sun4i_tcon0_mode_set_cpu()
288 	tcon->dclk_max_div = 127;  in sun4i_tcon0_mode_set_cpu()
290 	sun4i_tcon0_mode_set_common(tcon, mode);  in sun4i_tcon0_mode_set_cpu()
292 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,  in sun4i_tcon0_mode_set_cpu()
296 	regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,  in sun4i_tcon0_mode_set_cpu()
299 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,  in sun4i_tcon0_mode_set_cpu()
311 	regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);  in sun4i_tcon0_mode_set_cpu()
316 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,  in sun4i_tcon0_mode_set_cpu()
320 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,  in sun4i_tcon0_mode_set_cpu()
326 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,  in sun4i_tcon0_mode_set_cpu()
334 	regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,  in sun4i_tcon0_mode_set_cpu()
339 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,  in sun4i_tcon0_mode_set_cpu()
343 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,  in sun4i_tcon0_mode_set_lvds()  argument
351 	WARN_ON(!tcon->quirks->has_channel_0);  in sun4i_tcon0_mode_set_lvds()
353 	tcon->dclk_min_div = 7;  in sun4i_tcon0_mode_set_lvds()
354 	tcon->dclk_max_div = 7;  in sun4i_tcon0_mode_set_lvds()
355 	sun4i_tcon0_mode_set_common(tcon, mode);  in sun4i_tcon0_mode_set_lvds()
359 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,  in sun4i_tcon0_mode_set_lvds()
372 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,  in sun4i_tcon0_mode_set_lvds()
385 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,  in sun4i_tcon0_mode_set_lvds()
397 	regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);  in sun4i_tcon0_mode_set_lvds()
406 	regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);  in sun4i_tcon0_mode_set_lvds()
409 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,  in sun4i_tcon0_mode_set_lvds()
414 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);  in sun4i_tcon0_mode_set_lvds()
417 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,  in sun4i_tcon0_mode_set_rgb()  argument
424 	WARN_ON(!tcon->quirks->has_channel_0);  in sun4i_tcon0_mode_set_rgb()
426 	tcon->dclk_min_div = 6;  in sun4i_tcon0_mode_set_rgb()
427 	tcon->dclk_max_div = 127;  in sun4i_tcon0_mode_set_rgb()
428 	sun4i_tcon0_mode_set_common(tcon, mode);  in sun4i_tcon0_mode_set_rgb()
432 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,  in sun4i_tcon0_mode_set_rgb()
445 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,  in sun4i_tcon0_mode_set_rgb()
458 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,  in sun4i_tcon0_mode_set_rgb()
466 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,  in sun4i_tcon0_mode_set_rgb()
477 	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,  in sun4i_tcon0_mode_set_rgb()
482 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,  in sun4i_tcon0_mode_set_rgb()
487 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);  in sun4i_tcon0_mode_set_rgb()
490 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,  in sun4i_tcon1_mode_set()  argument
497 	WARN_ON(!tcon->quirks->has_channel_1);  in sun4i_tcon1_mode_set()
500 	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);  in sun4i_tcon1_mode_set()
504 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,  in sun4i_tcon1_mode_set()
513 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,  in sun4i_tcon1_mode_set()
518 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,  in sun4i_tcon1_mode_set()
523 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,  in sun4i_tcon1_mode_set()
528 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,  in sun4i_tcon1_mode_set()
536 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,  in sun4i_tcon1_mode_set()
562 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,  in sun4i_tcon1_mode_set()
570 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,  in sun4i_tcon1_mode_set()
575 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,  in sun4i_tcon1_mode_set()
580 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,  in sun4i_tcon_mode_set()  argument
593 		sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode);  in sun4i_tcon_mode_set()
596 		sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);  in sun4i_tcon_mode_set()
599 		sun4i_tcon0_mode_set_rgb(tcon, mode);  in sun4i_tcon_mode_set()
600 		sun4i_tcon_set_mux(tcon, 0, encoder);  in sun4i_tcon_mode_set()
604 		sun4i_tcon1_mode_set(tcon, mode);  in sun4i_tcon_mode_set()
605 		sun4i_tcon_set_mux(tcon, 1, encoder);  in sun4i_tcon_mode_set()
629 	struct sun4i_tcon *tcon = private;  in sun4i_tcon_handler()  local
630 	struct drm_device *drm = tcon->drm;  in sun4i_tcon_handler()
631 	struct sun4i_crtc *scrtc = tcon->crtc;  in sun4i_tcon_handler()
635 	regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);  in sun4i_tcon_handler()
646 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,  in sun4i_tcon_handler()
659 				  struct sun4i_tcon *tcon)  in sun4i_tcon_init_clocks()  argument
661 	tcon->clk = devm_clk_get(dev, "ahb");  in sun4i_tcon_init_clocks()
662 	if (IS_ERR(tcon->clk)) {  in sun4i_tcon_init_clocks()
664 		return PTR_ERR(tcon->clk);  in sun4i_tcon_init_clocks()
666 	clk_prepare_enable(tcon->clk);  in sun4i_tcon_init_clocks()
668 	if (tcon->quirks->has_channel_0) {  in sun4i_tcon_init_clocks()
669 		tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");  in sun4i_tcon_init_clocks()
670 		if (IS_ERR(tcon->sclk0)) {  in sun4i_tcon_init_clocks()
672 			return PTR_ERR(tcon->sclk0);  in sun4i_tcon_init_clocks()
676 	if (tcon->quirks->has_channel_1) {  in sun4i_tcon_init_clocks()
677 		tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");  in sun4i_tcon_init_clocks()
678 		if (IS_ERR(tcon->sclk1)) {  in sun4i_tcon_init_clocks()
680 			return PTR_ERR(tcon->sclk1);  in sun4i_tcon_init_clocks()
687 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)  in sun4i_tcon_free_clocks()  argument
689 	clk_disable_unprepare(tcon->clk);  in sun4i_tcon_free_clocks()
693 			       struct sun4i_tcon *tcon)  in sun4i_tcon_init_irq()  argument
705 			       dev_name(dev), tcon);  in sun4i_tcon_init_irq()
722 				  struct sun4i_tcon *tcon)  in sun4i_tcon_init_regmap()  argument
733 	tcon->regs = devm_regmap_init_mmio(dev, regs,  in sun4i_tcon_init_regmap()
735 	if (IS_ERR(tcon->regs)) {  in sun4i_tcon_init_regmap()
737 		return PTR_ERR(tcon->regs);  in sun4i_tcon_init_regmap()
741 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);  in sun4i_tcon_init_regmap()
742 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);  in sun4i_tcon_init_regmap()
743 	regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);  in sun4i_tcon_init_regmap()
746 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);  in sun4i_tcon_init_regmap()
747 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);  in sun4i_tcon_init_regmap()
953 	struct sun4i_tcon *tcon;  in sun4i_tcon_bind()  local
964 	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);  in sun4i_tcon_bind()
965 	if (!tcon)  in sun4i_tcon_bind()
967 	dev_set_drvdata(dev, tcon);  in sun4i_tcon_bind()
968 	tcon->drm = drm;  in sun4i_tcon_bind()
969 	tcon->dev = dev;  in sun4i_tcon_bind()
970 	tcon->id = engine->id;  in sun4i_tcon_bind()
971 	tcon->quirks = of_device_get_match_data(dev);  in sun4i_tcon_bind()
973 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");  in sun4i_tcon_bind()
974 	if (IS_ERR(tcon->lcd_rst)) {  in sun4i_tcon_bind()
976 		return PTR_ERR(tcon->lcd_rst);  in sun4i_tcon_bind()
979 	if (tcon->quirks->needs_edp_reset) {  in sun4i_tcon_bind()
994 	ret = reset_control_reset(tcon->lcd_rst);  in sun4i_tcon_bind()
1000 	if (tcon->quirks->supports_lvds) {  in sun4i_tcon_bind()
1008 		tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");  in sun4i_tcon_bind()
1009 		if (IS_ERR(tcon->lvds_rst)) {  in sun4i_tcon_bind()
1011 			return PTR_ERR(tcon->lvds_rst);  in sun4i_tcon_bind()
1012 		} else if (tcon->lvds_rst) {  in sun4i_tcon_bind()
1014 			reset_control_reset(tcon->lvds_rst);  in sun4i_tcon_bind()
1026 		if (tcon->quirks->has_lvds_alt) {  in sun4i_tcon_bind()
1027 			tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");  in sun4i_tcon_bind()
1028 			if (IS_ERR(tcon->lvds_pll)) {  in sun4i_tcon_bind()
1029 				if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {  in sun4i_tcon_bind()
1033 					return PTR_ERR(tcon->lvds_pll);  in sun4i_tcon_bind()
1041 		    (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {  in sun4i_tcon_bind()
1052 	ret = sun4i_tcon_init_clocks(dev, tcon);  in sun4i_tcon_bind()
1058 	ret = sun4i_tcon_init_regmap(dev, tcon);  in sun4i_tcon_bind()
1064 	if (tcon->quirks->has_channel_0) {  in sun4i_tcon_bind()
1065 		ret = sun4i_dclk_create(dev, tcon);  in sun4i_tcon_bind()
1072 	ret = sun4i_tcon_init_irq(dev, tcon);  in sun4i_tcon_bind()
1078 	tcon->crtc = sun4i_crtc_init(drm, engine, tcon);  in sun4i_tcon_bind()
1079 	if (IS_ERR(tcon->crtc)) {  in sun4i_tcon_bind()
1081 		ret = PTR_ERR(tcon->crtc);  in sun4i_tcon_bind()
1085 	if (tcon->quirks->has_channel_0) {  in sun4i_tcon_bind()
1094 				ret = sun4i_lvds_init(drm, tcon);  in sun4i_tcon_bind()
1098 			ret = sun4i_rgb_init(drm, tcon);  in sun4i_tcon_bind()
1105 	if (tcon->quirks->needs_de_be_mux) {  in sun4i_tcon_bind()
1116 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,  in sun4i_tcon_bind()
1118 				   tcon->id);  in sun4i_tcon_bind()
1119 		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,  in sun4i_tcon_bind()
1121 				   tcon->id);  in sun4i_tcon_bind()
1124 	list_add_tail(&tcon->list, &drv->tcon_list);  in sun4i_tcon_bind()
1129 	if (tcon->quirks->has_channel_0)  in sun4i_tcon_bind()
1130 		sun4i_dclk_free(tcon);  in sun4i_tcon_bind()
1132 	sun4i_tcon_free_clocks(tcon);  in sun4i_tcon_bind()
1134 	reset_control_assert(tcon->lcd_rst);  in sun4i_tcon_bind()
1141 	struct sun4i_tcon *tcon = dev_get_drvdata(dev);  in sun4i_tcon_unbind()  local
1143 	list_del(&tcon->list);  in sun4i_tcon_unbind()
1144 	if (tcon->quirks->has_channel_0)  in sun4i_tcon_unbind()
1145 		sun4i_dclk_free(tcon);  in sun4i_tcon_unbind()
1146 	sun4i_tcon_free_clocks(tcon);  in sun4i_tcon_unbind()
1182 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,  in sun4i_a10_tcon_set_mux()  argument
1201 			   0x3 << shift, tcon->id << shift);  in sun4i_a10_tcon_set_mux()
1206 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,  in sun5i_a13_tcon_set_mux()  argument
1219 	return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);  in sun5i_a13_tcon_set_mux()
1222 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,  in sun6i_tcon_set_mux()  argument
1242 			   0x3 << shift, tcon->id << shift);  in sun6i_tcon_set_mux()