378 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)  in dsi_write()  function
396 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
398 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
401 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
403 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
406 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);  in dw_mipi_dsi_phy_write()
440 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_phy_init()
441 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);  in dw_mipi_dsi_phy_init()
442 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_phy_init()
498 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |  in dw_mipi_dsi_phy_init()
625 	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);  in dw_mipi_message_config()
626 	dsi_write(dsi, DSI_CMD_MODE_CFG, val);  in dw_mipi_message_config()
643 	dsi_write(dsi, DSI_GEN_HDR, hdr_val);  in dw_mipi_dsi_gen_pkt_hdr_write()
700 			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);  in dw_mipi_dsi_dcs_long_write()
704 			dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);  in dw_mipi_dsi_dcs_long_write()
767 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_dsi_video_mode_config()
774 		dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_set_mode()
775 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_set_mode()
776 		dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_set_mode()
778 		dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_set_mode()
779 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);  in dw_mipi_dsi_set_mode()
781 		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);  in dw_mipi_dsi_set_mode()
782 		dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_set_mode()
788 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_disable()
789 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);  in dw_mipi_dsi_disable()
804 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_init()
805 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK  in dw_mipi_dsi_init()
807 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |  in dw_mipi_dsi_init()
836 	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));  in dw_mipi_dsi_dpi_config()
837 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);  in dw_mipi_dsi_dpi_config()
838 	dsi_write(dsi, DSI_DPI_CFG_POL, val);  in dw_mipi_dsi_dpi_config()
839 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)  in dw_mipi_dsi_dpi_config()
845 	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);  in dw_mipi_dsi_packet_handler_config()
851 	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));  in dw_mipi_dsi_video_packet_config()
856 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));  in dw_mipi_dsi_command_mode_config()
857 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);  in dw_mipi_dsi_command_mode_config()
858 	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_command_mode_config()
888 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
891 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
894 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
907 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);  in dw_mipi_dsi_vertical_timing_config()
908 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);  in dw_mipi_dsi_vertical_timing_config()
909 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);  in dw_mipi_dsi_vertical_timing_config()
910 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);  in dw_mipi_dsi_vertical_timing_config()
915 	dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)  in dw_mipi_dsi_dphy_timing_config()
918 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)  in dw_mipi_dsi_dphy_timing_config()
924 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |  in dw_mipi_dsi_dphy_interface_config()
932 	dsi_write(dsi, DSI_INT_MSK0, 0);  in dw_mipi_dsi_clear_err()
933 	dsi_write(dsi, DSI_INT_MSK1, 0);  in dw_mipi_dsi_clear_err()