92 		WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);  in sumo_gfx_clockgating_enable()
94 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);  in sumo_gfx_clockgating_enable()
95 		WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);  in sumo_gfx_clockgating_enable()
96 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);  in sumo_gfx_clockgating_enable()
129 	WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);  in sumo_program_git()
176 	WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),  in sumo_gfx_powergating_initialize()
182 	WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),  in sumo_gfx_powergating_initialize()
278 		WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);  in sumo_gfx_powergating_enable()
280 		WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);  in sumo_gfx_powergating_enable()
437 		WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);  in sumo_program_tp()
438 		WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);  in sumo_program_tp()
442 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);  in sumo_program_tp()
444 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);  in sumo_program_tp()
447 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);  in sumo_program_tp()
450 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);  in sumo_program_tp()
481 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_set_divider_value()
484 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_set_divider_value()
487 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_set_divider_value()
490 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_set_divider_value()
566 			WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);  in sumo_program_power_level()
572 			WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);  in sumo_program_power_level()
587 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_power_level_enable()
590 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_power_level_enable()
593 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_power_level_enable()
596 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),  in sumo_power_level_enable()
610 	WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);  in sumo_start_dpm()
615 	WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);  in sumo_stop_dpm()
621 		WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);  in sumo_set_forced_mode()
623 		WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);  in sumo_set_forced_mode()
729 	WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);  in sumo_set_forced_level()
776 	WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);  in sumo_enable_acpi_pm()
781 	WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);  in sumo_program_power_level_enter_state()
796 	WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);  in sumo_program_acpi_power_level()
797 	WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);  in sumo_program_acpi_power_level()
907 		WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);  in sumo_enable_sclk_ds()
912 	WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);  in sumo_program_bootup_at()
913 	WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);  in sumo_program_bootup_at()
918 	WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);  in sumo_reset_am()
923 	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);  in sumo_start_am()
956 		WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);  in sumo_enable_voltage_scaling()
957 		WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);  in sumo_enable_voltage_scaling()
959 		WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);  in sumo_enable_voltage_scaling()
960 		WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);  in sumo_enable_voltage_scaling()
966 	WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,  in sumo_override_cnb_thermal_events()
993 			WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);  in sumo_force_nbp_state()
995 			WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);  in sumo_force_nbp_state()
1172 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);  in sumo_set_thermal_temperature_range()
1173 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);  in sumo_set_thermal_temperature_range()