2287 						SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_power_containment_values()  argument
2310 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_power_containment_values()
2315 	smc_state->levels[0].dpm2.MaxPS = 0;  in si_populate_power_containment_values()
2316 	smc_state->levels[0].dpm2.NearTDPDec = 0;  in si_populate_power_containment_values()
2317 	smc_state->levels[0].dpm2.AboveSafeInc = 0;  in si_populate_power_containment_values()
2318 	smc_state->levels[0].dpm2.BelowSafeInc = 0;  in si_populate_power_containment_values()
2319 	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;  in si_populate_power_containment_values()
2369 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma…  in si_populate_power_containment_values()
2370 		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;  in si_populate_power_containment_values()
2371 		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;  in si_populate_power_containment_values()
2372 		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;  in si_populate_power_containment_values()
2373 		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);  in si_populate_power_containment_values()
2381 					 SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_sq_ramping_values()  argument
2392 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_sq_ramping_values()
2429 		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);  in si_populate_sq_ramping_values()
2430 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);  in si_populate_sq_ramping_values()
4961 			       SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_smc_sp()  argument
4968 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);  in si_populate_smc_sp()
4970 	smc_state->levels[ps->performance_level_count - 1].bSP =  in si_populate_smc_sp()
5085 			     SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_smc_t()  argument
5099 		smc_state->levels[0].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5103 	smc_state->levels[0].aT = cpu_to_be32(0);  in si_populate_smc_t()
5119 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;  in si_populate_smc_t()
5121 		smc_state->levels[i].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5126 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5188 					 SISLANDS_SMC_SWSTATE *smc_state)  in si_convert_power_state_to_smc()  argument
5206 			smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;  in si_convert_power_state_to_smc()
5212 		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;  in si_convert_power_state_to_smc()
5214 	smc_state->levelCount = 0;  in si_convert_power_state_to_smc()
5219 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;  in si_convert_power_state_to_smc()
5221 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;  in si_convert_power_state_to_smc()
5226 						    &smc_state->levels[i]);  in si_convert_power_state_to_smc()
5227 		smc_state->levels[i].arbRefreshState =  in si_convert_power_state_to_smc()
5234 			smc_state->levels[i].displayWatermark =  in si_convert_power_state_to_smc()
5238 			smc_state->levels[i].displayWatermark = (i < 2) ?  in si_convert_power_state_to_smc()
5242 			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;  in si_convert_power_state_to_smc()
5244 			smc_state->levels[i].ACIndex = 0;  in si_convert_power_state_to_smc()
5246 		smc_state->levelCount++;  in si_convert_power_state_to_smc()
5253 	si_populate_smc_sp(rdev, radeon_state, smc_state);  in si_convert_power_state_to_smc()
5255 	ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);  in si_convert_power_state_to_smc()
5259 	ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);  in si_convert_power_state_to_smc()
5263 	return si_populate_smc_t(rdev, radeon_state, smc_state);  in si_convert_power_state_to_smc()
5277 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()  local
5279 	memset(smc_state, 0, state_size);  in si_upload_sw_state()
5281 	ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);  in si_upload_sw_state()
5285 	ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,  in si_upload_sw_state()
5300 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()  local
5303 		memset(smc_state, 0, state_size);  in si_upload_ulv_state()
5305 		ret = si_populate_ulv_state(rdev, smc_state);  in si_upload_ulv_state()
5307 			ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,  in si_upload_ulv_state()