Lines Matching refs:rlc
5217 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5222 if (tmp != rlc) in si_update_rlc()
5223 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5279 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5285 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5685 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5693 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5717 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5729 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5781 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5782 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5787 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5788 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
6640 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6641 rdev->rlc.reg_list_size = in si_startup()
6644 rdev->rlc.cs_data = si_cs_data; in si_startup()