3772 	u32 reset_mask = 0;  in si_gpu_check_soft_reset()  local
3783 		reset_mask |= RADEON_RESET_GFX;  in si_gpu_check_soft_reset()
3787 		reset_mask |= RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3790 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3795 		reset_mask |= RADEON_RESET_RLC;  in si_gpu_check_soft_reset()
3800 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3805 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3810 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3813 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3819 		reset_mask |= RADEON_RESET_IH;  in si_gpu_check_soft_reset()
3822 		reset_mask |= RADEON_RESET_SEM;  in si_gpu_check_soft_reset()
3825 		reset_mask |= RADEON_RESET_GRBM;  in si_gpu_check_soft_reset()
3828 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3832 		reset_mask |= RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3835 		reset_mask |= RADEON_RESET_DISPLAY;  in si_gpu_check_soft_reset()
3840 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3843 	if (reset_mask & RADEON_RESET_MC) {  in si_gpu_check_soft_reset()
3844 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in si_gpu_check_soft_reset()
3845 		reset_mask &= ~RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3848 	return reset_mask;  in si_gpu_check_soft_reset()
3851 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in si_gpu_soft_reset()  argument
3857 	if (reset_mask == 0)  in si_gpu_soft_reset()
3860 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in si_gpu_soft_reset()
3878 	if (reset_mask & RADEON_RESET_DMA) {  in si_gpu_soft_reset()
3884 	if (reset_mask & RADEON_RESET_DMA1) {  in si_gpu_soft_reset()
3898 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {  in si_gpu_soft_reset()
3913 	if (reset_mask & RADEON_RESET_CP) {  in si_gpu_soft_reset()
3919 	if (reset_mask & RADEON_RESET_DMA)  in si_gpu_soft_reset()
3922 	if (reset_mask & RADEON_RESET_DMA1)  in si_gpu_soft_reset()
3925 	if (reset_mask & RADEON_RESET_DISPLAY)  in si_gpu_soft_reset()
3928 	if (reset_mask & RADEON_RESET_RLC)  in si_gpu_soft_reset()
3931 	if (reset_mask & RADEON_RESET_SEM)  in si_gpu_soft_reset()
3934 	if (reset_mask & RADEON_RESET_IH)  in si_gpu_soft_reset()
3937 	if (reset_mask & RADEON_RESET_GRBM)  in si_gpu_soft_reset()
3940 	if (reset_mask & RADEON_RESET_VMC)  in si_gpu_soft_reset()
3943 	if (reset_mask & RADEON_RESET_MC)  in si_gpu_soft_reset()
4085 	u32 reset_mask;  in si_asic_reset()  local
4092 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4094 	if (reset_mask)  in si_asic_reset()
4098 	si_gpu_soft_reset(rdev, reset_mask);  in si_asic_reset()
4100 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4103 	if (reset_mask && radeon_hard_reset)  in si_asic_reset()
4106 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4108 	if (!reset_mask)  in si_asic_reset()
4125 	u32 reset_mask = si_gpu_check_soft_reset(rdev);  in si_gfx_is_lockup()  local
4127 	if (!(reset_mask & (RADEON_RESET_GFX |  in si_gfx_is_lockup()