Lines Matching refs:WREG32
1628 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1629 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1634 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1635 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1637 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in si_mc_load_microcode()
1638 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in si_mc_load_microcode()
1644 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in si_mc_load_microcode()
1646 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in si_mc_load_microcode()
1650 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1651 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
1652 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in si_mc_load_microcode()
2000 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
2003 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
2435 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2436 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2443 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2444 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2448 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2451 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2452 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2724 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in si_tiling_mode_table_init()
2939 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in si_tiling_mode_table_init()
2960 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh()
3010 WREG32(SPI_STATIC_THREAD_MGMT_3, data); in si_setup_spi()
3084 WREG32(PA_SC_RASTER_CONFIG, data); in si_setup_rb()
3189 WREG32((0x2c14 + j), 0x00000000); in si_gpu_init()
3190 WREG32((0x2c18 + j), 0x00000000); in si_gpu_init()
3191 WREG32((0x2c1c + j), 0x00000000); in si_gpu_init()
3192 WREG32((0x2c20 + j), 0x00000000); in si_gpu_init()
3193 WREG32((0x2c24 + j), 0x00000000); in si_gpu_init()
3196 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in si_gpu_init()
3197 WREG32(SRBM_INT_CNTL, 1); in si_gpu_init()
3198 WREG32(SRBM_INT_ACK, 1); in si_gpu_init()
3202 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in si_gpu_init()
3274 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3275 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3276 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
3277 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3278 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3279 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3281 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3282 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3283 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3305 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in si_gpu_init()
3307 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in si_gpu_init()
3310 WREG32(SX_DEBUG_1, sx_debug_1); in si_gpu_init()
3312 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in si_gpu_init()
3314 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3319 WREG32(VGT_NUM_INSTANCES, 1); in si_gpu_init()
3321 WREG32(CP_PERFMON_CNTL, 0); in si_gpu_init()
3323 WREG32(SQ_CONFIG, 0); in si_gpu_init()
3325 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in si_gpu_init()
3328 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in si_gpu_init()
3331 WREG32(VGT_GS_VERTEX_REUSE, 16); in si_gpu_init()
3332 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in si_gpu_init()
3334 WREG32(CB_PERFCOUNTER0_SELECT0, 0); in si_gpu_init()
3335 WREG32(CB_PERFCOUNTER0_SELECT1, 0); in si_gpu_init()
3336 WREG32(CB_PERFCOUNTER1_SELECT0, 0); in si_gpu_init()
3337 WREG32(CB_PERFCOUNTER1_SELECT1, 0); in si_gpu_init()
3338 WREG32(CB_PERFCOUNTER2_SELECT0, 0); in si_gpu_init()
3339 WREG32(CB_PERFCOUNTER2_SELECT1, 0); in si_gpu_init()
3340 WREG32(CB_PERFCOUNTER3_SELECT0, 0); in si_gpu_init()
3341 WREG32(CB_PERFCOUNTER3_SELECT1, 0); in si_gpu_init()
3345 WREG32(HDP_MISC_CNTL, tmp); in si_gpu_init()
3348 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in si_gpu_init()
3350 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in si_gpu_init()
3463 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3467 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3468 WREG32(SCRATCH_UMSK, 0); in si_cp_enable()
3503 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3505 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3506 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3512 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3514 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3515 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3521 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3523 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3524 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3530 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3532 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3533 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3537 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3539 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3540 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3544 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3546 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3547 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3550 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3551 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3552 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3553 WREG32(CP_ME_RAM_RADDR, 0); in si_cp_load_microcode()
3653 WREG32(CP_SEM_WAIT_TIMER, 0x0); in si_cp_resume()
3654 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in si_cp_resume()
3657 WREG32(CP_RB_WPTR_DELAY, 0); in si_cp_resume()
3659 WREG32(CP_DEBUG, 0); in si_cp_resume()
3660 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3670 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3673 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3675 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3678 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3679 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3682 WREG32(SCRATCH_UMSK, 0xff); in si_cp_resume()
3685 WREG32(SCRATCH_UMSK, 0); in si_cp_resume()
3689 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3691 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3701 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3704 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3706 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3709 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3710 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3713 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3715 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3725 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3728 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3730 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3733 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3734 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3737 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3739 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3876 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
3882 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3888 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3950 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3956 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3964 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3970 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3989 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
3993 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4003 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4007 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
4016 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4020 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4024 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4028 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4045 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
4049 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4053 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4145 WREG32((0x2c14 + j), 0x00000000); in si_mc_program()
4146 WREG32((0x2c18 + j), 0x00000000); in si_mc_program()
4147 WREG32((0x2c1c + j), 0x00000000); in si_mc_program()
4148 WREG32((0x2c20 + j), 0x00000000); in si_mc_program()
4149 WREG32((0x2c24 + j), 0x00000000); in si_mc_program()
4151 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in si_mc_program()
4159 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in si_mc_program()
4161 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in si_mc_program()
4163 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in si_mc_program()
4165 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in si_mc_program()
4169 WREG32(MC_VM_FB_LOCATION, tmp); in si_mc_program()
4171 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
4172 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in si_mc_program()
4173 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in si_mc_program()
4174 WREG32(MC_VM_AGP_BASE, 0); in si_mc_program()
4175 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in si_mc_program()
4176 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in si_mc_program()
4275 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in si_pcie_gart_tlb_flush()
4278 WREG32(VM_INVALIDATE_REQUEST, 1); in si_pcie_gart_tlb_flush()
4293 WREG32(MC_VM_MX_L1_TLB_CNTL, in si_pcie_gart_enable()
4301 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
4307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4308 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4312 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in si_pcie_gart_enable()
4313 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in si_pcie_gart_enable()
4314 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4315 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4317 WREG32(VM_CONTEXT0_CNTL2, 0); in si_pcie_gart_enable()
4318 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4321 WREG32(0x15D4, 0); in si_pcie_gart_enable()
4322 WREG32(0x15D8, 0); in si_pcie_gart_enable()
4323 WREG32(0x15DC, 0); in si_pcie_gart_enable()
4327 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in si_pcie_gart_enable()
4328 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4335 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in si_pcie_gart_enable()
4338 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in si_pcie_gart_enable()
4343 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4345 WREG32(VM_CONTEXT1_CNTL2, 4); in si_pcie_gart_enable()
4346 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4383 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
4384 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
4386 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in si_pcie_gart_disable()
4389 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
4393 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
4394 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
5152 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5184 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5197 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5209 WREG32(RLC_CNTL, data); in si_halt_rlc()
5223 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5236 WREG32(DMA_PG, data); in si_enable_dma_pg()
5243 WREG32(DMA_PGFSM_WRITE, 0x00002000); in si_init_dma_pg()
5244 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); in si_init_dma_pg()
5247 WREG32(DMA_PGFSM_WRITE, 0); in si_init_dma_pg()
5257 WREG32(RLC_TTOP_D, tmp); in si_enable_gfx_cgpg()
5261 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5265 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5269 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5279 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5283 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
5285 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5292 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_init_gfx_cgpg()
5343 WREG32(RLC_PG_AO_CU_MASK, tmp); in si_init_ao_cu_mask()
5348 WREG32(RLC_MAX_PG_CU, tmp); in si_init_ao_cu_mask()
5361 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); in si_enable_cgcg()
5365 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_cgcg()
5366 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_cgcg()
5367 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); in si_enable_cgcg()
5373 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); in si_enable_cgcg()
5388 WREG32(RLC_CGCG_CGLS_CTRL, data); in si_enable_cgcg()
5400 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5406 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5412 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5416 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5417 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5418 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); in si_enable_mgcg()
5425 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5430 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5435 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5439 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5440 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5441 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); in si_enable_mgcg()
5460 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5472 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5505 WREG32(mc_cg_registers[i], data); in si_enable_mc_ls()
5522 WREG32(mc_cg_registers[i], data); in si_enable_mc_mgcg()
5541 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5542 WREG32(DMA_CLK_CTRL + offset, 0x00000100); in si_enable_dma_mgcg()
5553 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5558 WREG32(DMA_CLK_CTRL + offset, data); in si_enable_dma_mgcg()
5594 WREG32(HDP_HOST_PATH_CNTL, data); in si_enable_hdp_mgcg()
5610 WREG32(HDP_MEM_POWER_LS, data); in si_enable_hdp_ls()
5781 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5782 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5787 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5788 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5808 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5811 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5817 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5826 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
5853 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5857 WREG32(SPI_LB_CU_MASK, 0x00ff); in si_enable_lbpw()
5876 WREG32(RLC_RL_BASE, 0); in si_rlc_resume()
5877 WREG32(RLC_RL_SIZE, 0); in si_rlc_resume()
5878 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
5879 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); in si_rlc_resume()
5880 WREG32(RLC_LB_CNTR_INIT, 0); in si_rlc_resume()
5881 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in si_rlc_resume()
5883 WREG32(RLC_MC_CNTL, 0); in si_rlc_resume()
5884 WREG32(RLC_UCODE_CNTL, 0); in si_rlc_resume()
5896 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5897 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); in si_rlc_resume()
5903 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5904 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in si_rlc_resume()
5907 WREG32(RLC_UCODE_ADDR, 0); in si_rlc_resume()
5923 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5924 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5935 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
5936 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5938 WREG32(IH_RB_RPTR, 0); in si_disable_interrupts()
5939 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
5951 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
5952 WREG32(CP_INT_CNTL_RING1, 0); in si_disable_interrupt_state()
5953 WREG32(CP_INT_CNTL_RING2, 0); in si_disable_interrupt_state()
5955 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5957 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5958 WREG32(GRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5959 WREG32(SRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5961 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5963 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
5966 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in si_disable_interrupt_state()
5997 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in si_irq_init()
6005 WREG32(INTERRUPT_CNTL, interrupt_cntl); in si_irq_init()
6007 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
6018 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in si_irq_init()
6019 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
6021 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6024 WREG32(IH_RB_RPTR, 0); in si_irq_init()
6025 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6032 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
6099 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
6100 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); in si_irq_set()
6101 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); in si_irq_set()
6103 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6104 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
6106 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in si_irq_set()
6121 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set()
6132 WREG32(CG_THERMAL_INT, thermal_int); in si_irq_set()
6160 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in si_irq_ack()
6166 WREG32(VBLANK_STATUS + crtc_offsets[j], in si_irq_ack()
6169 WREG32(VLINE_STATUS + crtc_offsets[j], in si_irq_ack()
6226 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
6360 WREG32(SRBM_INT_ACK, 0x1); in si_irq_process()
6433 WREG32(IH_RB_RPTR, rptr); in si_irq_process()
6986 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in si_get_gpu_clock_counter()
7395 WREG32(THM_CLK_CNTL, data); in si_program_aspm()
7401 WREG32(MISC_CLK_CNTL, data); in si_program_aspm()
7406 WREG32(CG_CLKPIN_CNTL, data); in si_program_aspm()
7411 WREG32(CG_CLKPIN_CNTL_2, data); in si_program_aspm()
7417 WREG32(MPLL_BYPASSCLK_SEL, data); in si_program_aspm()
7422 WREG32(SPLL_CNTL_MODE, data); in si_program_aspm()