2521 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2530 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2539 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2548 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2557 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2566 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2575 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2584 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2593 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2602 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2611 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2620 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2629 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2638 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2647 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2656 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2665 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2674 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2683 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2692 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2701 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2710 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2719 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2736 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2745 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2754 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2763 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2772 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2781 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2790 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2799 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2808 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2817 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2826 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2835 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2844 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2853 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2862 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2871 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2880 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2889 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2898 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2907 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2916 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2925 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2934 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()