Lines Matching refs:link_width_cntl
2023 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2046 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2047 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2048 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2049 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2050 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2051 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2052 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2054 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2056 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2058 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2059 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2092 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2095 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2097 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2098 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()