318 	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),  in rv6xx_set_engine_spread_spectrum_clk_s()
325 	WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),  in rv6xx_set_engine_spread_spectrum_clk_v()
333 		WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),  in rv6xx_enable_engine_spread_spectrum()
336 		WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),  in rv6xx_enable_engine_spread_spectrum()
343 	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);  in rv6xx_set_memory_spread_spectrum_clk_s()
349 	WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);  in rv6xx_set_memory_spread_spectrum_clk_v()
356 		WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);  in rv6xx_enable_memory_spread_spectrum()
358 		WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);  in rv6xx_enable_memory_spread_spectrum()
365 		WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);  in rv6xx_enable_dynamic_spread_spectrum()
367 		WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);  in rv6xx_enable_dynamic_spread_spectrum()
374 		WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),  in rv6xx_memory_clock_entry_enable_post_divider()
377 		WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);  in rv6xx_memory_clock_entry_enable_post_divider()
383 	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),  in rv6xx_memory_clock_entry_set_post_divider()
390 	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),  in rv6xx_memory_clock_entry_set_feedback_divider()
397 	WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),  in rv6xx_memory_clock_entry_set_reference_divider()
403 	WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);  in rv6xx_vid_response_set_brt()
408 	WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);  in rv6xx_enable_engine_feedback_and_reference_sync()
735 		WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
737 		WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
740 		WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
742 		WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
777 		WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_lowest_entry()
779 		WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);  in rv6xx_program_backbias_stepping_parameters_lowest_entry()
992 		WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);  in rv6xx_enable_display_gap()
994 		WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);  in rv6xx_enable_display_gap()
1174 		WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,  in rv6xx_enable_backbias()
1177 		WREG32_P(GENERAL_PWRMGT, 0,  in rv6xx_enable_backbias()
1213 	WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),  in rv6xx_set_sw_voltage_to_safe()
1225 	WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),  in rv6xx_set_sw_voltage_to_low()
1238 		WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);  in rv6xx_set_safe_backbias()
1240 		WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);  in rv6xx_set_safe_backbias()
1259 		WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);  in rv6xx_enable_dynamic_voltage_control()
1261 		WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);  in rv6xx_enable_dynamic_voltage_control()
1268 		WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);  in rv6xx_enable_dynamic_backbias_control()
1270 		WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);  in rv6xx_enable_dynamic_backbias_control()
1381 		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);  in rv6xx_set_dpm_event_sources()
1383 			WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);  in rv6xx_set_dpm_event_sources()
1385 		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);  in rv6xx_set_dpm_event_sources()
1489 		WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);  in rv6xx_reset_lvtm_data_sync()
1491 		WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);  in rv6xx_reset_lvtm_data_sync()