Lines Matching refs:crtc_offset

51 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
53 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
54 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
55 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
57 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
59 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
77 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); in avivo_crtc_load_lut()
89 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
92 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
93 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
96 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
97 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
99 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
100 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce4_crtc_load_lut()
102 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
107 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce4_crtc_load_lut()
124 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
127 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
129 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
131 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
135 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
137 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
138 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
139 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
141 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
142 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
143 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
145 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
146 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce5_crtc_load_lut()
148 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
153 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
159 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
164 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
167 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
170 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
174 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
179 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()