Lines Matching refs:tmp
196 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
199 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
201 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
389 uint32_t tmp; in radeon_legacy_set_engine_clock() local
396 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
397 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
398 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
400 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
406 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
407 tmp |= RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
408 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
412 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
413 tmp |= RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
414 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
418 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_set_engine_clock()
419 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); in radeon_legacy_set_engine_clock()
420 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; in radeon_legacy_set_engine_clock()
421 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
424 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
425 tmp &= ~RADEON_SPLL_PVG_MASK; in radeon_legacy_set_engine_clock()
427 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
429 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
430 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
432 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
433 tmp &= ~RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
438 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
439 tmp &= ~RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
440 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
444 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
445 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
449 tmp |= 1; in radeon_legacy_set_engine_clock()
452 tmp |= 2; in radeon_legacy_set_engine_clock()
455 tmp |= 3; in radeon_legacy_set_engine_clock()
458 tmp |= 4; in radeon_legacy_set_engine_clock()
461 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
465 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
466 tmp |= RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
467 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
474 uint32_t tmp; in radeon_legacy_set_clock_gating() local
478 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
482 tmp &= in radeon_legacy_set_clock_gating()
486 tmp &= in radeon_legacy_set_clock_gating()
492 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
496 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
497 tmp &= in radeon_legacy_set_clock_gating()
511 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
512 tmp |= in radeon_legacy_set_clock_gating()
515 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
517 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
518 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
519 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
520 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
522 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
523 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
525 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
527 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
528 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
541 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
543 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
544 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
547 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | in radeon_legacy_set_clock_gating()
550 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
552 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
553 tmp &= in radeon_legacy_set_clock_gating()
567 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
568 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
570 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
571 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
572 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
573 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
575 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
576 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
578 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
580 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
581 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
594 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
596 tmp = RREG32_PLL(RADEON_MCLK_MISC); in radeon_legacy_set_clock_gating()
597 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | in radeon_legacy_set_clock_gating()
599 WREG32_PLL(RADEON_MCLK_MISC, tmp); in radeon_legacy_set_clock_gating()
601 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
602 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
605 tmp &= ~(RADEON_FORCEON_YCLKA | in radeon_legacy_set_clock_gating()
613 if ((tmp & R300_DISABLE_MC_MCLKA) && in radeon_legacy_set_clock_gating()
614 (tmp & R300_DISABLE_MC_MCLKB)) { in radeon_legacy_set_clock_gating()
616 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
620 tmp &= in radeon_legacy_set_clock_gating()
623 tmp &= in radeon_legacy_set_clock_gating()
626 tmp &= ~(R300_DISABLE_MC_MCLKA | in radeon_legacy_set_clock_gating()
631 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
633 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
634 tmp &= ~(R300_SCLK_FORCE_VAP); in radeon_legacy_set_clock_gating()
635 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
636 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
639 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
640 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
643 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
646 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
648 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | in radeon_legacy_set_clock_gating()
652 tmp |= (RADEON_ENGIN_DYNCLK_MODE | in radeon_legacy_set_clock_gating()
654 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
657 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_clock_gating()
658 tmp |= RADEON_SCLK_DYN_START_CNTL; in radeon_legacy_set_clock_gating()
659 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_clock_gating()
665 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
667 tmp &= ~RADEON_SCLK_FORCEON_MASK; in radeon_legacy_set_clock_gating()
679 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
680 tmp |= RADEON_SCLK_FORCE_VIP; in radeon_legacy_set_clock_gating()
683 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
688 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
689 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
697 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
699 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
709 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
710 tmp |= RADEON_TCL_BYPASS_DISABLE; in radeon_legacy_set_clock_gating()
711 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
716 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
717 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
725 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
728 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
729 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
732 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
738 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
739 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
746 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
749 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
750 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
758 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
760 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
761 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
762 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
764 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
765 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
768 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
770 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
771 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
785 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
788 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
789 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
791 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
793 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
794 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
802 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
804 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
805 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
806 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
808 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
809 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
813 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
815 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
816 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
819 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
821 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
822 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
836 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
838 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
839 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); in radeon_legacy_set_clock_gating()
840 tmp |= RADEON_SCLK_FORCE_SE; in radeon_legacy_set_clock_gating()
843 tmp |= (RADEON_SCLK_FORCE_RB | in radeon_legacy_set_clock_gating()
856 tmp |= (RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
863 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
869 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
870 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
873 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
878 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
879 tmp &= ~(RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
881 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
888 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
889 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
890 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
894 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
895 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
903 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
906 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
907 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
909 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()