105 	struct radeon_pll *p1pll = &rdev->clock.p1pll;  in radeon_read_clocks_OF()  local
117 	p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;  in radeon_read_clocks_OF()
118 	p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;  in radeon_read_clocks_OF()
119 	if (p1pll->reference_div < 2)  in radeon_read_clocks_OF()
120 		p1pll->reference_div = 12;  in radeon_read_clocks_OF()
121 	p2pll->reference_div = p1pll->reference_div;  in radeon_read_clocks_OF()
125 		p1pll->pll_in_min = 100;  in radeon_read_clocks_OF()
126 		p1pll->pll_in_max = 1350;  in radeon_read_clocks_OF()
127 		p1pll->pll_out_min = 20000;  in radeon_read_clocks_OF()
128 		p1pll->pll_out_max = 50000;  in radeon_read_clocks_OF()
134 		p1pll->pll_in_min = 40;  in radeon_read_clocks_OF()
135 		p1pll->pll_in_max = 500;  in radeon_read_clocks_OF()
136 		p1pll->pll_out_min = 12500;  in radeon_read_clocks_OF()
137 		p1pll->pll_out_max = 35000;  in radeon_read_clocks_OF()
146 	spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;  in radeon_read_clocks_OF()
179 	struct radeon_pll *p1pll = &rdev->clock.p1pll;  in radeon_get_clock_info()  local
194 		if (p1pll->reference_div < 2) {  in radeon_get_clock_info()
198 					p1pll->reference_div =  in radeon_get_clock_info()
201 					p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;  in radeon_get_clock_info()
202 				if (p1pll->reference_div < 2)  in radeon_get_clock_info()
203 					p1pll->reference_div = 12;  in radeon_get_clock_info()
205 				p1pll->reference_div = 12;  in radeon_get_clock_info()
227 				p1pll->reference_freq = 1432;  in radeon_get_clock_info()
232 				p1pll->reference_freq = 2700;  in radeon_get_clock_info()
237 			p1pll->reference_div =  in radeon_get_clock_info()
239 			if (p1pll->reference_div < 2)  in radeon_get_clock_info()
240 				p1pll->reference_div = 12;  in radeon_get_clock_info()
241 			p2pll->reference_div = p1pll->reference_div;  in radeon_get_clock_info()
244 				p1pll->pll_in_min = 100;  in radeon_get_clock_info()
245 				p1pll->pll_in_max = 1350;  in radeon_get_clock_info()
246 				p1pll->pll_out_min = 20000;  in radeon_get_clock_info()
247 				p1pll->pll_out_max = 50000;  in radeon_get_clock_info()
253 				p1pll->pll_in_min = 40;  in radeon_get_clock_info()
254 				p1pll->pll_in_max = 500;  in radeon_get_clock_info()
255 				p1pll->pll_out_min = 12500;  in radeon_get_clock_info()
256 				p1pll->pll_out_max = 35000;  in radeon_get_clock_info()
276 		p1pll->min_post_div = 2;  in radeon_get_clock_info()
277 		p1pll->max_post_div = 0x7f;  in radeon_get_clock_info()
278 		p1pll->min_frac_feedback_div = 0;  in radeon_get_clock_info()
279 		p1pll->max_frac_feedback_div = 9;  in radeon_get_clock_info()
285 		p1pll->min_post_div = 1;  in radeon_get_clock_info()
286 		p1pll->max_post_div = 16;  in radeon_get_clock_info()
287 		p1pll->min_frac_feedback_div = 0;  in radeon_get_clock_info()
288 		p1pll->max_frac_feedback_div = 0;  in radeon_get_clock_info()
306 	p1pll->min_ref_div = 2;  in radeon_get_clock_info()
307 	p1pll->max_ref_div = 0x3ff;  in radeon_get_clock_info()
308 	p1pll->min_feedback_div = 4;  in radeon_get_clock_info()
309 	p1pll->max_feedback_div = 0x7ff;  in radeon_get_clock_info()
310 	p1pll->best_vco = 0;  in radeon_get_clock_info()