248 		WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);  in r600_gfx_clockgating_enable()
250 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);  in r600_gfx_clockgating_enable()
270 		WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);  in r600_dynamicpm_enable()
272 		WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);  in r600_dynamicpm_enable()
278 		WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);  in r600_enable_thermal_protection()
280 		WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);  in r600_enable_thermal_protection()
285 	WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);  in r600_enable_acpi_pm()
291 		WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);  in r600_enable_dynamic_pcie_gen2()
293 		WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);  in r600_enable_dynamic_pcie_gen2()
307 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);  in r600_enable_sclk_control()
309 		WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);  in r600_enable_sclk_control()
315 		WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);  in r600_enable_mclk_control()
317 		WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);  in r600_enable_mclk_control()
323 		WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);  in r600_enable_spll_bypass()
325 		WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);  in r600_enable_spll_bypass()
362 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);  in r600_select_td()
364 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);  in r600_select_td()
366 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);  in r600_select_td()
368 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);  in r600_select_td()
378 	WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);  in r600_set_tpu()
383 	WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);  in r600_set_tpc()
388 	WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);  in r600_set_sstu()
393 	WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);  in r600_set_sst()
398 	WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);  in r600_set_git()
403 	WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);  in r600_set_fctu()
408 	WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);  in r600_set_fct()
413 	WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);  in r600_set_ctxcgtt3d_rphc()
418 	WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);  in r600_set_ctxcgtt3d_rsdc()
423 	WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);  in r600_set_vddc3d_oorsu()
428 	WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);  in r600_set_vddc3d_oorphc()
433 	WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);  in r600_set_vddc3d_oorsdc()
438 	WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);  in r600_set_mpll_lock_time()
443 	WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);  in r600_set_mpll_reset_time()
450 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable()
453 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable()
461 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable_pulse_skipping()
464 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable_pulse_skipping()
472 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable_post_divider()
475 		WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),  in r600_engine_clock_entry_enable_post_divider()
482 	WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),  in r600_engine_clock_entry_set_post_divider()
489 	WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),  in r600_engine_clock_entry_set_reference_divider()
496 	WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),  in r600_engine_clock_entry_set_feedback_divider()
503 	WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),  in r600_engine_clock_entry_set_step_time()
509 	WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);  in r600_vid_rt_set_ssu()
514 	WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);  in r600_vid_rt_set_vru()
519 	WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);  in r600_vid_rt_set_vrt()
568 		WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,  in r600_power_level_enable()
571 		WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,  in r600_power_level_enable()
580 	WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),  in r600_power_level_set_voltage_index()
589 	WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),  in r600_power_level_set_mem_clock_index()
598 	WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),  in r600_power_level_set_eng_clock_index()
611 	WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);  in r600_power_level_set_watermark_id()
622 	WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);  in r600_power_level_set_pcie_gen2()
646 	WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),  in r600_power_level_set_enter_index()
755 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);  in r600_set_thermal_temperature_range()
756 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);  in r600_set_thermal_temperature_range()
757 	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);  in r600_set_thermal_temperature_range()